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| dsPIC33F Family Data Sheet High-Performance, 16-Bit Digital Signal Controllers (c) 2007 Microchip Technology Inc. DS70165E Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS70165E-page ii (c) 2007 Microchip Technology Inc. dsPIC33F High-Performance, 16-bit Digital Signal Controllers Operating Range: * DC - 40 MIPS (40 MIPS @ 3.0-3.6V, -40C to +85C) * Industrial temperature range (-40C to +85C) Digital I/O: * * * * * Up to 85 programmable digital I/O pins Wake-up/Interrupt-on-Change on up to 24 pins Output pins can drive from 3.0V to 3.6V All digital input pins are 5V tolerant 4 mA sink on all I/O pins High-Performance DSC CPU: * * * * * * * * * * * * * * Modified Harvard architecture C compiler optimized instruction set 16-bit wide data path 24-bit wide instructions Linear program memory addressing up to 4M instruction words Linear data memory addressing up to 64 Kbytes 83 base instructions: mostly 1 word/1 cycle Sixteen 16-bit General Purpose Registers Two 40-bit accumulators: - With rounding and saturation options Flexible and powerful addressing modes: - Indirect, Modulo and Bit-Reversed Software stack 16 x 16 fractional/integer multiply operations 32/16 and 16/16 divide operations Single-cycle multiply and accumulate: - Accumulator write back for DSP operations - Dual data fetch Up to 16-bit shifts for up to 40-bit data On-Chip Flash and SRAM: * Flash program memory, up to 256 Kbytes * Data SRAM, up to 30 Kbytes (includes 2 Kbytes of DMA RAM): System Management: * Flexible clock options: - External, crystal, resonator, internal RC - Fully integrated PLL - Extremely low jitter PLL * Power-up Timer * Oscillator Start-up Timer/Stabilizer * Watchdog Timer with its own RC oscillator * Fail-Safe Clock Monitor * Reset by multiple sources Power Management: * On-chip 2.5V voltage regulator * Switch between clock sources in real time * Idle, Sleep and Doze modes with fast wake-up * Direct Memory Access (DMA): * 8-channel hardware DMA: * 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA: - Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing) * Most peripherals support DMA Timers/Capture/Compare/PWM: * Timer/Counters, up to nine 16-bit timers: - Can pair up to make four 32-bit timers - 1 timer runs as Real-Time Clock with external 32.768 kHz oscillator - Programmable prescaler * Input Capture (up to 8 channels): - Capture on up, down or both edges - 16-bit capture input functions - 4-deep FIFO on each capture * Output Compare (up to 8 channels): - Single or Dual 16-Bit Compare mode - 16-bit Glitchless PWM mode Interrupt Controller: * * * * * * 5-cycle latency 118 interrupt vectors Up to 67 available interrupt sources Up to 5 external interrupts 7 programmable priority levels 5 processor exceptions (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 1 dsPIC33F Communication Modules: * 3-wire SPI (up to 2 modules): - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes * I2CTM (up to 2 modules): - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing - Bus collision detection and arbitration - Integrated signal conditioning - Slave address masking * UART (up to 2 modules): - Interrupt on address bit detect - Interrupt on UART error - Wake-up on Start bit from Sleep mode - 4-character TX and RX FIFO buffers - LIN bus support - IrDA(R) encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS * Data Converter Interface (DCI) module: - Codec interface - Supports I2S and AC'97 protocols - Up to 16-bit data words, up to 16 words per frame - 4-word deep TX and RX buffers * Enhanced CAN (ECANTM module) 2.0B active (up to 2 modules): - Up to 8 transmit and up to 32 receive buffers - 16 receive filters and 3 masks - Loopback, Listen Only and Listen All Messages modes for diagnostics and bus monitoring - Wake-up on CAN message - Automatic processing of Remote Transmission Requests - FIFO mode using DMA - DeviceNetTM addressing support Motor Control Peripherals: * Motor Control PWM (up to 8 channels): - 4 duty cycle generators - Independent or Complementary mode - Programmable dead time and output polarity - Edge or center-aligned - Manual output override control - Up to 2 Fault inputs - Trigger for ADC conversions - PWM frequency for 16-bit resolution (@ 40 MIPS) = 1220 Hz for Edge-Aligned mode, 610 Hz for Center-Aligned mode - PWM frequency for 11-bit resolution (@ 40 MIPS) = 39.1 kHz for Edge-Aligned mode, 19.55 kHz for Center-Aligned mode * Quadrature Encoder Interface module: - Phase A, Phase B and index pulse input - 16-bit up/down position counter - Count direction status - Position Measurement (x2 and x4) mode - Programmable digital noise filters on inputs - Alternate 16-bit Timer/Counter mode - Interrupt on position counter rollover/underflow Analog-to-Digital Converters (ADCs): * Up to two ADC modules in a device * 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion: - 2, 4 or 8 simultaneous samples - Up to 32 input channels with auto-scanning - Conversion start can be manual or synchronized with 1 of 4 trigger sources - Conversion possible in Sleep mode - 2 LSb max integral nonlinearity - 1 LSb max differential nonlinearity CMOS Flash Technology: * * * * * Low-power, high-speed Flash technology Fully static design 3.3V (10%) operating voltage Industrial temperature Low-power consumption Packaging: * 100-pin TQFP (14x14x1 mm and 12x12x1 mm) * 80-pin TQFP (12x12x1 mm) * 64-pin TQFP (10x10x1 mm) Note: See the device variant tables for exact peripheral features per device. DS70165E-page 2 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F dsPIC33F PRODUCT FAMILIES There are two device subfamilies within the dsPIC33F family of devices. They are the General Purpose Family and the Motor Control Family. The General Purpose Family is ideal for a wide variety of 16-bit MCU embedded applications. The variants with codec interfaces are well-suited for speech and audio processing applications. The Motor Control Family supports a variety of motor control applications, such as brushless DC motors, single and 3-phase induction motors and switched reluctance motors. These products are also well-suited for Uninterrupted Power Supply (UPS), inverters, Switched mode power supplies, power factor correction and also for controlling the power management module in servers, telecommunication equipment and other industrial equipment. The device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams. dsPIC33F General Purpose Family Variants Output Compare Std. PWM Program Flash Pins Memory (Kbyte) 64 64 100 64 80 100 64 64 100 64 80 100 64 100 100 64 64 64 64 64 64 128 128 128 128 128 128 256 256 256 I/O Pins (Max)(2) 53 53 85 53 69 85 53 53 85 53 69 85 53 85 85 Input Capture 16-bit Timer Enhanced CAN Codec Interface UART I2CTM ADC Device RAM (Kbyte)(1) SPI Packages dsPIC33FJ64GP206 dsPIC33FJ64GP306 dsPIC33FJ64GP310 dsPIC33FJ64GP706 dsPIC33FJ64GP708 dsPIC33FJ64GP710 DSPIC33FJ128GP206 dsPIC33FJ128GP306 dsPIC33FJ128GP310 dsPIC33FJ128GP706 dsPIC33FJ128GP708 dsPIC33FJ128GP710 dsPIC33FJ256GP506 dsPIC33FJ256GP510 dsPIC33FJ256GP710 Note 1: 2: 8 16 16 16 16 16 8 16 16 16 16 16 16 16 30 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ADC, 18 ch 1 ADC, 18 ch 1 ADC, 32 ch 2 ADC, 18 ch 2 ADC, 24 ch 2 ADC, 32 ch 1 ADC, 18 ch 1 ADC, 18 ch 1 ADC, 32 ch 2 ADC, 18 ch 2 ADC, 24 ch 2 ADC, 32 ch 1 ADC, 18 ch 1 ADC, 32 ch 2 ADC, 32 ch 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 2 2 2 1 2 2 2 2 2 2 2 2 0 0 0 2 2 2 0 0 0 2 2 2 1 1 2 PT PT PF, PT PT PT PF, PT PT PT PF, PT PT PT PF, PT PT PF, PT PF, PT RAM size is inclusive of 2 Kbytes DMA RAM. Maximum I/O pin count includes pins shared by the peripheral functions. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 3 dsPIC33F Pin Diagrams 64-Pin TQFP CSDO/RG13 CSDI/RG12 CSCK/RG14 RG0 RG1 RF1 RF0 VDD VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 COFS/RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/T5CK/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/VREF-/CN3/RB1 PGD3/EMUD3/AN0/VREF+/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ64GP206 DSPIC33FJ128GP206 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TDI/AN13/RB13 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 U2RX/CN17/RF4 U2TX/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DS70165E-page 4 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F Pin Diagrams (Continued) 64-Pin TQFP CSDO/RG13 CSDI/RG12 CSCK/RG14 RG0 RG1 RF1 RF0 VDD VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 COFS/RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/T5CK/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/VREF-/CN3/RB1 PGD3/EMUD3/AN0/VREF+/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ64GP306 dsPIC33FJ128GP306 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 (c) 2007 Microchip Technology Inc. PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TDI/AN13/RB13 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Preliminary DS70165E-page 5 dsPIC33F Pin Diagrams (Continued) 64-Pin TQFP CSDO/RG13 CSDI/RG12 CSCK/RG14 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 COFS/RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/T5CK/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/VREF-/CN3/RB1 PGD3/EMUD3/AN0/VREF+/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ256GP506 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TDI/AN13/RB13 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DS70165E-page 6 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F Pin Diagrams (Continued) 64-Pin TQFP CSDO/RG13 CSDI/RG12 CSCK/RG14 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 COFS/RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/T5CK/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/VREF-/CN3/RB1 PGD3/EMUD3/AN0/VREF+/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ64GP706 dsPIC33FJ128GP706 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 (c) 2007 Microchip Technology Inc. PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TDI/AN13/RB13 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Preliminary DS70165E-page 7 dsPIC33F Pin Diagrams (Continued) 80-Pin TQFP AN23/CN23/RA7 AN22/CN22/RA6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/RD7 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 OC7/CN15/RD6 CSDO/RG13 CSDI/RG12 CSCK/RG14 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 COFS/RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD TMS/AN20/INT1/RA12 TDO/AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 60 59 58 57 56 55 54 53 52 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 SDA2/INT4/RA3 SCL2/INT3/RA2 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 dsPIC33FJ64GP708 dsPIC33FJ128GP708 51 50 49 48 47 46 45 44 43 42 41 40 U2TX/CN18/RF5 IC7/U1CTS/CN20/RD14 PGC1/EMUC1/AN6/OCFA/RB6 DS70165E-page 8 Preliminary AN15/OCFB/CN12/RB15 PGD1/EMUD1/AN7/RB7 IC8/U1RTS/CN21/RD15 U2CTS/AN8/RB8 U2RTS/AN14/RB14 U2RX/CN17/RF4 VREF-/RA9 TCK/AN12/RB12 TDI/AN13/RB13 VREF+/RA10 AN10/RB10 AN11/RB11 AN9/RB9 AVDD AVSS VDD VSS (c) 2007 Microchip Technology Inc. dsPIC33F Pin Diagrams (Continued) 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AN28/RE4 AN27/RE3 AN26/RE2 CSDO/RG13 CSDI/RG12 CSCK/RG14 AN25/RE1 AN24/RE0 AN23/CN23/RA7 AN22/CN22/RA6 RG0 RG1 RF1 RF0 VDD VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 COFS/RG15 VDD AN29/RE5 AN30/RE6 AN31/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/INT1/RA12 AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 VSS PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 dsPIC33FJ64GP310 dsPIC33FJ128GP310 63 62 61 60 59 58 57 56 55 54 53 52 51 (c) 2007 Microchip Technology Inc. PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 VREF-/RA9 VREF+/RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15 VSS VDD IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Preliminary DS70165E-page 9 dsPIC33F Pin Diagrams (Continued) 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 AN28/RE4 AN27/RE3 AN26/RE2 CSDO/RG13 CSDI/RG12 CSCK/RG14 AN25/RE1 AN24/RE0 AN23/CN23/RA7 AN22/CN22/RA6 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 COFS/RG15 VDD AN29/RE5 AN30/RE6 AN31/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/INT1/RA12 AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VSS PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 dsPIC33FJ256GP510 63 62 61 60 59 58 57 56 55 54 53 52 51 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 VREF-/RA9 VREF+/RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15 VSS VDD IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DS70165E-page 10 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F Pin Diagrams (Continued) 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AN28/RE4 AN27/RE3 AN26/RE2 CSDO/RG13 CSDI/RG12 CSCK/RG14 AN25/RE1 AN24/RE0 AN23/CN23/RA7 AN22/CN22/RA6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 COFS/RG15 VDD AN29/RE5 AN30/RE6 AN31/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/INT1/RA12 AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 VSS PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 dsPIC33FJ64GP710 dsPIC33FJ128GP710 dsPIC33FJ256GP710 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 (c) 2007 Microchip Technology Inc. PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 VREF-/RA9 VREF+/RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15 VSS VDD IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Preliminary DS70165E-page 11 dsPIC33F dsPIC33F Motor Control Family Variants Quadrature Encoder Interface Motor Control PWM Output Compare Std. PWM Progra m Flash RAM Pins Memory (Kbyte)(1) (Kbyte) I/O Pins (Max)(2) 53 69 85 53 85 53 85 53 69 85 85 85 Codec Interface Enhanced CAN Input Capture Timer 16-bit UART Device I2CTM ADC SPI Packages dsPIC33FJ64MC506 dsPIC33FJ64MC508 dsPIC33FJ64MC510 dsPIC33FJ64MC706 dsPIC33FJ64MC710 dsPIC33FJ128MC506 dsPIC33FJ128MC510 dsPIC33FJ128MC706 dsPIC33FJ128MC708 dsPIC33FJ128MC710 dsPIC33FJ256MC510 dsPIC33FJ256MC710 Note 1: 2: 64 80 100 64 100 64 100 64 80 100 100 100 64 64 64 64 64 128 128 128 128 128 256 256 8 8 8 16 16 8 8 16 16 16 16 30 9 9 9 9 9 9 9 9 9 9 9 9 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 ADC, 16 ch 1 ADC, 18 ch 1 ADC, 24 ch 2 ADC, 16 ch 2 ADC, 24 ch 1 ADC, 16 ch 1 ADC, 24 ch 2 ADC, 16 ch 2 ADC, 18 ch 2 ADC, 24 ch 1 ADC, 24 ch 2 ADC, 24 ch 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 2 1 1 1 2 2 1 2 PT PT PF, PT PT PF, PT PT PF, PT PT PT PF, PT PF, PT PF, PT RAM size is inclusive of 2 Kbytes DMA RAM. Maximum I/O pin count includes pins shared by the peripheral functions. DS70165E-page 12 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F Pin Diagrams 64-Pin TQFP PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/T5CK/CN11/RG9 VSS VDD AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 AN3/INDX/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/VREF-/CN3/RB1 PGD3/EMUD3/AN0/VREF+/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/UPDN/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 dsPIC33FJ64MC506 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/FLTB/INT2/RD9 IC1/FLTA/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 (c) 2007 Microchip Technology Inc. PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TDI/AN13/RB13 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 U2RX/CN17/RF4 U2TX/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Preliminary DS70165E-page 13 dsPIC33F Pin Diagrams (Continued) 64-Pin TQFP PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/T5CK/CN11/RG9 VSS VDD AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 AN3/INDX/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/VREF-/CN3/RB1 PGD3/EMUD3/AN0/VREF+/CN2/RB0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/UPDN/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ128MC506 dsPIC33FJ64MC506 dsPIC33FJ128MC706 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/FLTB/INT2/RD9 IC1/FLTA/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TDI/AN13/RB13 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DS70165E-page 14 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F Pin Diagrams (Continued) 80-Pin TQFP RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/UPDN/RD7 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 OC7/CN15/RD6 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 RG0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD TMS/FLTA/INT1/RE8 TDO/FLTB/INT2/RE9 AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4 AN3/INDX/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 SDA2/INT4/RA3 SCL2/INT3/RA2 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 dsPIC33FJ64MC508 50 49 48 47 46 45 44 43 42 41 U2RX/CN17/RF4 AN15/OCFB/CN12/RB15 IC7/U1CTS/CN20/RD14 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 (c) 2007 Microchip Technology Inc. Preliminary IC8/U1RTS/CN21/RD15 U2CTS/AN8/RB8 U2RTS/AN14/RB14 TCK/AN12/RB12 U2TX/CN18/RF5 VREF+/RA10 VREF-/RA9 AN10/RB10 AN11/RB11 TDI/AN13/RB13 AN9/RB9 AVDD AVSS VDD VSS DS70165E-page 15 dsPIC33F Pin Diagrams (Continued) 80-Pin TQFP CRX2/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/UPDN/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 IC5/RD12 OC4/RD3 OC3/RD2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 OC2/RD1 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD TMS/FLTA/INT1/RE8 TDO/FLTB/INT2/RE9 AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4 AN3/INDX/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 SDA2/INT4/RA3 SCL2/INT3/RA2 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 dsPIC33FJ128MC708 50 49 48 47 46 45 44 43 42 41 40 U2TX/CN18/RF5 AN15/OCFB/CN12/RB15 U2RTS/AN14/RB14 AN10/RB10 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 U2CTS/AN8/RB8 IC7/U1CTS/CN20/RD14 DS70165E-page 16 Preliminary IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 TCK/AN12/RB12 TDI/AN13/RB13 VREF+/RA10 VREF-/RA9 AN9/RB9 AN11/RB11 AVDD AVSS VDD VSS (c) 2007 Microchip Technology Inc. dsPIC33F Pin Diagrams (Continued) 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 CSDO/RG13 CSDI/RG12 CSCK/RG14 PWM1H/RE1 PWM1L/RE0 AN23/CN23/RA7 AN22/CN22/RA6 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/UPDN//CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 COFS/RG15 VDD PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/FLTA/INT1/RE8 AN21/FLTB/INT2/RE9 AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4 AN3/INDX/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 VSS PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 RA3 RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 dsPIC33FJ64MC510 63 62 61 60 59 58 57 56 55 54 53 52 51 (c) 2007 Microchip Technology Inc. PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 VREF-/RA9 VREF+/RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15 VSS VDD IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Preliminary DS70165E-page 17 dsPIC33F Pin Diagrams (Continued) 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 CSDO/RG13 CSDI/RG12 CSCK/RG14 PWM1H/RE1 PWM1L/RE0 AN23/CN23/RA7 AN22/CN22/RA6 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/UPDN//CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 COFS/RG15 VDD PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/FLTA/INT1/RE8 AN21/FLTB/INT2/RE9 AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4 AN3/INDX/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 VSS PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 dsPIC33FJ128MC510 dsPIC33FJ256MC510 63 62 61 60 59 58 57 56 55 54 53 52 51 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 VREF-/RA9 VREF+/RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15 VSS VDD IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DS70165E-page 18 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F Pin Diagrams (Continued) 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 CSDO/RG13 CSDI/RG12 CSCK/RG14 PWM1H/RE1 PWM1L/RE0 AN23/CN23/RA7 AN22/CN22/RA6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/UPDN//CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 COFS/RG15 VDD PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/FLTA/INT1/RE8 AN21/FLTB/INT2/RE9 AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4 AN3/INDX/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VSS PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 dsPIC33FJ64MC710 dsPIC33FJ128MC710 dsPIC33FJ256MC710 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 (c) 2007 Microchip Technology Inc. PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 VREF-/RA9 VREF+/RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15 VSS VDD IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Preliminary DS70165E-page 19 dsPIC33F Table of Contents dsPIC33F Product Families ................................................................................................................................................................... 3 1.0 Device Overview ........................................................................................................................................................................ 23 2.0 CPU............................................................................................................................................................................................ 27 3.0 Memory Organization ................................................................................................................................................................. 39 4.0 Flash Program Memory.............................................................................................................................................................. 77 5.0 Resets ....................................................................................................................................................................................... 83 6.0 Interrupt Controller ..................................................................................................................................................................... 87 7.0 Direct Memory Access (DMA) .................................................................................................................................................. 135 8.0 Oscillator Configuration ............................................................................................................................................................ 149 9.0 Power-Saving Features............................................................................................................................................................ 157 10.0 I/O Ports ................................................................................................................................................................................... 159 11.0 Timer1 ...................................................................................................................................................................................... 161 12.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ............................................................................................................................ 163 13.0 Input Capture............................................................................................................................................................................ 169 14.0 Output Compare....................................................................................................................................................................... 171 15.0 Motor Control PWM Module ..................................................................................................................................................... 175 16.0 Quadrature Encoder Interface (QEI) Module ........................................................................................................................... 197 17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 205 18.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 213 19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 223 20.0 Enhanced CAN Module............................................................................................................................................................ 231 21.0 Data Converter Interface (DCI) Module.................................................................................................................................... 261 22.0 10-bit/12-bit Analog-to-Digital Converter (ADC) ....................................................................................................................... 275 23.0 Special Features ...................................................................................................................................................................... 289 24.0 Instruction Set Summary .......................................................................................................................................................... 297 25.0 Development Support............................................................................................................................................................... 305 26.0 Electrical Characteristics .......................................................................................................................................................... 309 27.0 Packaging Information.............................................................................................................................................................. 351 Appendix A: Revision History............................................................................................................................................................. 357 Index ................................................................................................................................................................................................. 359 The Microchip Web Site ..................................................................................................................................................................... 365 Customer Change Notification Service .............................................................................................................................................. 365 Customer Support .............................................................................................................................................................................. 365 Reader Response .............................................................................................................................................................................. 366 Product Identification System ............................................................................................................................................................ 367 DS70165E-page 20 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 21 dsPIC33F NOTES: DS70165E-page 22 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 1.0 Note: DEVICE OVERVIEW This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). This document contains device specific information for the following devices: * * * * * * * * * * * * * * * * * * * * * * * * * * * dsPIC33FJ64GP206 dsPIC33FJ64GP306 dsPIC33FJ64GP310 dsPIC33FJ64GP706 dsPIC33FJ64GP708 dsPIC33FJ64GP710 DSPIC33FJ128GP206 dsPIC33FJ128GP306 dsPIC33FJ128GP310 dsPIC33FJ128GP706 dsPIC33FJ128GP708 dsPIC33FJ128GP710 dsPIC33FJ256GP506 dsPIC33FJ256GP510 dsPIC33FJ256GP710 dsPIC33FJ64MC506 dsPIC33FJ64MC508 dsPIC33FJ64MC510 dsPIC33FJ64MC706 dsPIC33FJ64MC710 dsPIC33FJ128MC506 dsPIC33FJ128MC510 dsPIC33FJ128MC706 dsPIC33FJ128MC708 dsPIC33FJ128MC710 dsPIC33FJ256MC510 dsPIC33FJ256MC710 This makes these families suitable for a wide variety of high-performance digital signal control application. The devices are pin compatible with the PIC24H family of devices, and also share a very high degree of compatibility with the dsPIC30F family devices. This allows easy migration between device families as may be necessitated by the specific functionality, computational resource and system cost requirements of the application. The dsPIC33F device family employs a powerful 16-bit architecture that seamlessly integrates the control features of a Microcontroller (MCU) with the computational capabilities of a Digital Signal Processor (DSP). The resulting functionality is ideal for applications that rely on high-speed, repetitive computations, as well as control. The DSP engine, dual 40-bit accumulators, hardware support for division operations, barrel shifter, 17 x 17 multiplier, a large array of 16-bit working registers and a wide variety of data addressing modes, together provide the dsPIC33F Central Processing Unit (CPU) with extensive mathematical processing capability. Flexible and deterministic interrupt handling, coupled with a powerful array of peripherals, renders the dsPIC33F devices suitable for control applications. Further, Direct Memory Access (DMA) enables overhead-free transfer of data between several peripherals and a dedicated DMA RAM. Reliable, field programmable Flash program memory ensures scalability of applications that use dsPIC33F devices. Figure 1-1 shows a general block diagram of the various core and peripheral modules in the dsPIC33F family of devices, while Table 1-1 lists the functions of the various pins shown in the pinout diagrams. The dsPIC33F General Purpose and Motor Control Families of devices include devices with a wide range of pin counts (64, 80 and 100), different program memory sizes (64 Kbytes, 128 Kbytes and 256 Kbytes) and different RAM sizes (8 Kbytes, 16 Kbytes and 30 Kbytes) (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 23 dsPIC33F FIGURE 1-1: PSV & Table Data Access Control Block Interrupt Controller 8 16 dsPIC33F GENERAL BLOCK DIAGRAM Y Data Bus X Data Bus PORTA 16 16 16 Data Latch Data Latch Y RAM Address Latch DMA 16 16 Controller PORTC 16 DMA RAM PORTB 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic X RAM Address Latch 23 Address Latch Address Generator Units Program Memory Address Bus Data Latch 24 ROM Latch 16 Literal Data EA MUX PORTD 16 Instruction Decode & Control Control Signals to Various Blocks Timing Generation FRC/LPRC Oscillators Precision Band Gap Reference Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Instruction Reg 16 PORTE DSP Engine 16 x 16 W Register Array 16 PORTF OSC2/CLKO OSC1/CLKI Divide Support 16-bit ALU 16 PORTG VDDCORE/VCAP VDD, VSS MCLR Timers 1-9 PWM QEI DCI ADC1,2 ECAN1,2 IC1-8 OC/ PWM1-8 CN1-23 SPI1,2 I2C1,2 UART1,2 Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features present on each device. DS70165E-page 24 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F TABLE 1-1: Pin Name AN0-AN31 AVDD AVSS CLKI CLKO PINOUT I/O DESCRIPTIONS Pin Type I P P I O Buffer Type Analog P P Analog input channels. Positive supply for analog modules. Ground reference for analog modules. Description ST/CMOS External clock source input. Always associated with OSC1 pin function. -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. ST ST ST ST -- ST -- ST -- ST ST ST ST ST ST ST ST ST ST CMOS ST ST ST ST ST ST ST -- -- -- -- -- -- -- -- ST ST ST -- Input change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. Data Converter Interface frame synchronization pin. Data Converter Interface serial clock input/output pin. Data Converter Interface serial data input pin. Data Converter Interface serial data output pin. ECAN1 bus receive pin. ECAN1 bus transmit pin. ECAN2 bus receive pin. ECAN2 bus transmit pin. Data I/O pin for programming/debugging communication channel 1. Clock input pin for programming/debugging communication channel 1. Data I/O pin for programming/debugging communication channel 2. Clock input pin for programming/debugging communication channel 2. Data I/O pin for programming/debugging communication channel 3. Clock input pin for programming/debugging communication channel 3. Capture inputs 1 through 8. Quadrature Encoder Index Pulse input. Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. Position Up/Down Counter Direction State. External interrupt 0. External interrupt 1. External interrupt 2. External interrupt 3. External interrupt 4. PWM Fault A input. PWM Fault B input. PWM 1 low output. PWM 1 high output. PWM 2 low output. PWM 2 high output. PWM 3 low output. PWM 3 high output. PWM 4 low output. PWM 4 high output. Master Clear (Reset) input. This pin is an active-low Reset to the device. Compare Fault A input (for Compare Channels 1, 2, 3 and 4). Compare Fault B input (for Compare Channels 5, 6, 7 and 8). Compare outputs 1 through 8. CN0-CN23 COFS CSCK CSDI CSDO C1RX C1TX C2RX C2TX PGD1/EMUD1 PGC1/EMUC1 PGD2/EMUD2 PGC2/EMUC2 PGD3/EMUD3 PGC3/EMUC3 IC1-IC8 INDX QEA QEB UPDN INT0 INT1 INT2 INT3 INT4 FLTA FLTB PWM1L PWM1H PWM2L PWM2H PWM3L PWM3H PWM4L PWM4H MCLR OCFA OCFB OC1-OC8 OSC1 OSC2 Legend: I I/O I/O I O I O I O I/O I I/O I I/O I I I I I O I I I I I I I O O O O O O O O I/P I I O I I/O ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. CMOS = CMOS compatible input or output; Analog = Analog input ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 25 dsPIC33F TABLE 1-1: Pin Name RA0-RA7 RA9-RA10 RA12-RA15 RB0-RB15 RC1-RC4 RC12-RC15 RD0-RD15 RE0-RE9 RF0-RF8 RF12-RF13 RG0-RG3 RG6-RG9 RG12-RG15 SCK1 SDI1 SDO1 SS1 SCK2 SDI2 SDO2 SS2 SCL1 SDA1 SCL2 SDA2 SOSCI SOSCO TMS TCK TDI TDO T1CK T2CK T3CK T4CK T5CK T6CK T7CK T8CK T9CK U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX VDD VDDCORE VSS VREF+ VREFLegend: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O I/O I/O I O I/O I/O I/O I/O I/O I O I I I O I I I I I I I I I I O I O I O I O P P P I I Buffer Type ST ST ST ST ST ST ST ST ST ST ST ST ST ST -- ST ST ST -- ST ST ST ST ST PORTA is a bidirectional I/O port. Description PORTB is a bidirectional I/O port. PORTC is a bidirectional I/O port. PORTD is a bidirectional I/O port. PORTE is a bidirectional I/O port. PORTF is a bidirectional I/O port. PORTG is a bidirectional I/O port. Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for SPI2. SPI2 data in. SPI2 data out. SPI2 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Synchronous serial clock input/output for I2C2. Synchronous serial data input/output for I2C2. ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. -- 32.768 kHz low-power oscillator crystal output. ST ST ST -- ST ST ST ST ST ST ST ST ST ST -- ST -- ST -- ST -- -- -- -- Analog Analog JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. Timer6 external clock input. Timer7 external clock input. Timer8 external clock input. Timer9 external clock input. UART1 clear to send. UART1 ready to send. UART1 receive. UART1 transmit. UART2 clear to send. UART2 ready to send. UART2 receive. UART2 transmit. Positive supply for peripheral logic and I/O pins. CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. CMOS = CMOS compatible input or output; Analog = Analog input ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power DS70165E-page 26 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 2.0 Note: CPU This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). Overhead-free circular buffers (Modulo Addressing mode) are supported in both X and Y address spaces. The Modulo Addressing removes the software boundary checking overhead for DSP algorithms. Furthermore, the X AGU circular addressing can be used with any of the MCU class of instructions. The X AGU also supports Bit-Reversed Addressing to greatly simplify input or output data reordering for radix-2 FFT algorithms. The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. The data space also includes 2 Kbytes of DMA RAM, which is primarily used for DMA data transfers, but may be used as general purpose RAM. The dsPIC33F CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for DSP. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space. The actual amount of program memory implemented varies by device. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any point. The dsPIC33F devices have sixteen, 16-bit working registers in the programmer's model. Each of the working registers can serve as a data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls. The dsPIC33F instruction set has two classes of instructions: MCU and DSP. These two instruction classes are seamlessly integrated into a single CPU. The instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the dsPIC33F is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle. A block diagram of the CPU is shown in Figure 2-1, and the programmer's model for the dsPIC33F is shown in Figure 2-2. 2.2 DSP Engine Overview The DSP engine features a high-speed, 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. The barrel shifter is capable of shifting a 40-bit value, up to 16 bits right or left, in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. The MAC instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two W registers and accumulating and optionally saturating the result in the same cycle. This instruction functionality requires that the RAM memory data space be split for these instructions and linear for all others. Data space partitioning is achieved in a transparent and flexible manner through dedicating certain working registers to each address space. 2.3 Special MCU Features 2.1 Data Addressing Overview The dsPIC33F features a 17-bit by 17-bit, single-cycle multiplier that is shared by both the MCU ALU and DSP engine. The multiplier can perform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed-sign multiplication, it also achieves accurate results for special operations, such as (-1.0) x (-1.0). The dsPIC33F supports 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data. A 40-bit barrel shifter is used to perform up to a 16-bit, left or right shift in a single cycle. The barrel shifter can be used by both MCU and DSP instructions. The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred to as X and Y data memory. Each memory block has its own independent Address Generation Unit (AGU). The MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one linear data space. Certain DSP instructions operate through the X and Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y data space boundary is device-specific. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 27 dsPIC33F FIGURE 2-1: PSV & Table Data Access Control Block Interrupt Controller 8 16 dsPIC33F CPU CORE BLOCK DIAGRAM Y Data Bus X Data Bus 16 16 16 Data Latch Data Latch DMA Y RAM Address Latch RAM 16 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic X RAM Address Latch 23 16 Address Latch 16 DMA Controller Address Generator Units Program Memory Address Bus Data Latch 24 ROM Latch 16 Literal Data 16 EA MUX Instruction Decode & Control Instruction Reg 16 Control Signals to Various Blocks DSP Engine 16 x 16 W Register Array 16 Divide Support 16-bit ALU 16 To Peripheral Modules DS70165E-page 28 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F FIGURE 2-2: dsPIC33F PROGRAMMER'S MODEL D15 W0/WREG W1 W2 W3 W4 DSP Operand Registers W5 W6 W7 W8 DSP Address Registers W9 W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer Working Registers DO Shadow D0 PUSH.S Shadow Legend SPLIM AD39 DSP Accumulators PC22 AccA AccB PC0 0 7 TBLPAG 7 PSVPAG 0 Program Space Visibility Page Address 15 RCOUNT 15 DCOUNT 22 DOSTART 22 DOEND 15 CORCON 0 0 0 0 0 Data Table Page Address AD31 Stack Pointer Limit Register AD15 AD0 Program Counter REPEAT Loop Counter DO Loop Counter DO Loop Start Address DO Loop End Address Core Configuration Register OA OB SA SB OAB SAB DA SRH DC IPL2 IPL1 IPL0 RA SRL N OV Z C STATUS Register (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 29 dsPIC33F 2.4 CPU Control Registers SR: CPU STATUS REGISTER R-0 OB R/C-0 SA(1) R/C-0 SB(1) R-0 OAB R/C-0 SAB R -0 DA R/W-0 DC bit 8 R/W-0(3) IPL<2:0> bit 7 Legend: C = Clear only bit S = Set only bit `1' = Bit is set bit 15 R = Readable bit W = Writable bit `0' = Bit is cleared OA: Accumulator A Overflow Status bit 1 = Accumulator A overflowed 0 = Accumulator A has not overflowed OB: Accumulator B Overflow Status bit 1 = Accumulator B overflowed 0 = Accumulator B has not overflowed SA: Accumulator A Saturation `Sticky' Status bit(1) 1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated SB: Accumulator B Saturation `Sticky' Status bit(1) 1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated OAB: OA || OB Combined Accumulator Overflow Status bit 1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed SAB: SA || SB Combined Accumulator `Sticky' Status bit 1 = Accumulators A or B are saturated or have been saturated at some time in the past 0 = Neither Accumulator A or B are saturated Note: bit 9 This bit may be read or cleared (not set). Clearing this bit will clear SA and SB. DA: DO Loop Active bit 1 = DO loop in progress 0 = DO loop not in progress DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred This bit may be read or cleared (not set). The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1. The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). U = Unimplemented bit, read as `0' -n = Value at POR x = Bit is unknown (2) REGISTER 2-1: R-0 OA bit 15 R/W-0(2) R/W-0(3) R-0 RA R/W-0 N R/W-0 OV R/W-0 Z R/W-0 C bit 0 bit 14 bit 13 bit 12 bit 11 bit 10 bit 8 Note 1: 2: 3: DS70165E-page 30 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 2-1: bit 7-5 SR: CPU STATUS REGISTER (CONTINUED) IPL<2:0>: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) OV: MCU ALU Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of the magnitude which causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: MCU ALU Zero bit 1 = An operation which affects the Z bit has set it at some time in the past 0 = The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result) C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred This bit may be read or cleared (not set). The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1. The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: 3: (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 31 dsPIC33F REGISTER 2-2: U-0 -- bit 15 R/W-0 SATA bit 7 Legend: R = Readable bit 0' = Bit is cleared bit 15-13 bit 12 CORCON: CORE CONTROL REGISTER U-0 -- U-0 -- R/W-0 US R/W-0 EDT(1) R-0 R-0 DL<2:0> R-0 bit 8 R/W-0 SATB R/W-1 SATDW R/W-0 ACCSAT R/C-0 IPL3(2) R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 C = Clear only bit W = Writable bit `x = Bit is unknown -n = Value at POR `1' = Bit is set U = Unimplemented bit, read as `0' bit 11 bit 10-8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Unimplemented: Read as `0' US: DSP Multiply Unsigned/Signed Control bit 1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed EDT: Early DO Loop Termination Control bit(1) 1 = Terminate executing DO loop at end of current loop iteration 0 = No effect DL<2:0>: DO Loop Nesting Level Status bits 111 = 7 DO loops active * * 001 = 1 DO loop active 000 = 0 DO loops active SATA: AccA Saturation Enable bit 1 = Accumulator A saturation enabled 0 = Accumulator A saturation disabled SATB: AccB Saturation Enable bit 1 = Accumulator B saturation enabled 0 = Accumulator B saturation disabled SATDW: Data Space Write from DSP Engine Saturation Enable bit 1 = Data space write saturation enabled 0 = Data space write saturation disabled ACCSAT: Accumulator Saturation Mode Select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space RND: Rounding Mode Select bit 1 = Biased (conventional) rounding enabled 0 = Unbiased (convergent) rounding enabled IF: Integer or Fractional Multiplier Mode Select bit 1 = Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops This bit will always read as `0'. The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. Note 1: 2: DS70165E-page 32 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 2.5 Arithmetic Logic Unit (ALU) The dsPIC33F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2's complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. Refer to the "dsPIC30F/33F Programmer's Reference Manual" (DS70157) for information on the SR bits affected by each instruction. The dsPIC33F CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit-divisor division. 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. 2.6 DSP Engine The DSP engine consists of a high-speed, 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/subtracter (with two target accumulators, round and saturation logic). The dsPIC33F is a single-cycle, instruction flow architecture; therefore, concurrent operation of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources may be used concurrently by the same instruction (e.g., ED, EDAC). The DSP engine also has the capability to perform inherent accumulator-to-accumulator operations which require no additional data. These instructions are ADD, SUB and NEG. The DSP engine has various options selected through various bits in the CPU Core Control register (CORCON), as listed below: 1. 2. 3. 4. 5. 6. 7. Fractional or integer DSP multiply (IF). Signed or unsigned DSP multiply (US). Conventional or convergent rounding (RND). Automatic saturation on/off for AccA (SATA). Automatic saturation on/off for AccB (SATB). Automatic saturation on/off for writes to data memory (SATDW). Accumulator Saturation mode selection (ACCSAT). 2.5.1 MULTIPLIER Using the high-speed 17-bit x 17-bit multiplier of the DSP engine, the ALU supports unsigned, signed or mixed-sign operation in several MCU multiplication modes: 1. 2. 3. 4. 5. 6. 7. 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned 2.5.2 DIVIDER The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: A block diagram of the DSP engine is shown in Figure 2-3. TABLE 2-1: DSP INSTRUCTIONS SUMMARY Algebraic Operation A=0 A = (x - y)2 A = A + (x - y)2 A = A + (x * y) A = A + x2 No change in A A=x*y A=x2 A=-x*y A=A-x*y ACC Write Back Yes No No Yes No Yes No No No Yes Instruction CLR ED EDAC MAC MAC MOVSAC MPY MPY MPY.N MSC (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 33 dsPIC33F FIGURE 2-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out 40-bit Accumulator A 40-bit Accumulator B Saturate Carry/Borrow In Adder Negate S a 40 Round t 16 u Logic r a t e 40 40 40 Barrel Shifter 16 40 Sign-Extend Y Data Bus 32 Zero Backfill 33 32 16 17-bit Multiplier/Scaler 16 16 To/From W Array DS70165E-page 34 Preliminary (c) 2007 Microchip Technology Inc. X Data Bus dsPIC33F 2.6.1 MULTIPLIER 2.6.2.1 The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17-bit x 17-bit multiplier/scaler is a 33-bit value which is sign-extended to 40 bits. Integer data is inherently represented as a signed two's complement value, where the MSb is defined as a sign bit. Generally speaking, the range of an N-bit two's complement integer is -2N-1 to 2N-1 - 1. For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including `0'. For a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,647 (0x7FFF FFFF). When the multiplier is configured for fractional multiplication, the data is represented as a two's complement fraction, where the MSb is defined as a sign bit and the radix point is implied to lie just after the sign bit (QX format). The range of an N-bit two's complement fraction with this implied radix point is -1.0 to (1 - 21-N). For a 16-bit fraction, the Q15 data range is -1.0 (0x8000) to 0.999969482 (0x7FFF) including `0' and has a precision of 3.01518x10-5. In Fractional mode, the 16 x 16 multiply operation generates a 1.31 product which has a precision of 4.65661 x 10-10. The same multiplier is used to support the MCU multiply instructions which include integer 16-bit signed, unsigned and mixed sign multiplies. The MUL instruction may be directed to use byte or word sized operands. Byte operands will direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the W array. Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true, or complement data into the other input. In the case of addition, the carry/borrow input is active-high and the other input is true data (not complemented), whereas in the case of subtraction, the carry/borrow input is active-low and the other input is complemented. The adder/subtracter generates Overflow Status bits, SA/SB and OA/OB, which are latched and reflected in the STATUS register: * Overflow from bit 39: this is a catastrophic overflow in which the sign of the accumulator is destroyed. * Overflow into guard bits 32 through 39: this is a recoverable overflow. This bit is set whenever all the guard bits are not identical to each other. The adder has an additional saturation block which controls accumulator data saturation, if selected. It uses the result of the adder, the Overflow Status bits described above and the SAT 2.6.2 DATA ACCUMULATORS AND ADDER/SUBTRACTER 4. The data accumulator consists of a 40-bit adder/subtracter with automatic sign extension logic. It can select one of two accumulators (A or B) as its pre-accumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter prior to accumulation. 5. 6. The OA and OB bits are modified each time data passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the corresponding Overflow Trap Flag Enable bits (OVATE, OVBTE) in the INTCON1 register (refer to Section 6.0 "Interrupt Controller") are set. This allows the user to take immediate action, for example, to correct system gain. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 35 dsPIC33F The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and, thus, indicate that a catastrophic overflow has occurred. If the COVTE bit in the INTCON1 register is set, SA and SB bits will generate an arithmetic warning trap when saturation is disabled. The Overflow and Saturation Status bits can optionally be viewed in the STATUS Register (SR) as the logical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). This allows programmers to check one bit in the STATUS register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. This would be useful for complex number arithmetic which typically uses both the accumulators. The device supports three Saturation and Overflow modes: 1. Bit 39 Overflow and Saturation: When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7FFFFFFFFF), or maximally negative 9.31 value (0x8000000000), into the target accumulator. The SA or SB bit is set and remains set until cleared by the user. This is referred to as `super saturation' and provides protection against erroneous data or unexpected algorithm problems (e.g., gain calculations). Bit 31 Overflow and Saturation: When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF), or maximally negative 1.31 value (0x0080000000), into the target accumulator. The SA or SB bit is set and remains set until cleared by the user. When this Saturation mode is in effect, the guard bits are not used (so the OA, OB or OAB bits are never set). Bit 39 Catastrophic Overflow: The bit 39 Overflow Status bit from the adder is used to set the SA or SB bit, which remains set until cleared by the user. No saturation operation is performed and the accumulator is allowed to overflow (destroying its sign). If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. 2.6.2.2 Accumulator `Write Back' The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instruction into data space memory. The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported: 1. W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a 1.15 fraction. [W13]+ = 2, Register Indirect with Post-Increment: The rounded contents of the non-target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write). 2. 2.6.2.3 Round Logic The round logic is a combinational block which performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND bit in the CORCON register. It generates a 16-bit, 1.15 data value which is passed to the data space write saturation logic. If rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the least significant word is simply discarded. Conventional rounding zero-extends bit 15 of the accumulator and adds it to the ACCxH word (bits 16 through 31 of the accumulator). If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000 included), ACCxH is incremented. If ACCxL is between 0x0000 and 0x7FFF, ACCxH is left unchanged. A consequence of this algorithm is that over a succession of random rounding operations, the value tends to be biased slightly positive. Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when ACCxL equals 0x8000. In this case, the Least Significant bit (bit 16 of the accumulator) of ACCxH is examined. If it is `1', ACCxH is incremented. If it is `0', ACCxH is not modified. Assuming that bit 16 is effectively random in nature, this scheme removes any rounding bias that may accumulate. The SAC and SAC.R instructions store either a truncated (SAC), or rounded (SAC.R) version of the contents of the target accumulator to data memory via the X bus, subject to data saturation (see Section 2.6.2.4 "Data Space Write Saturation"). For the MAC class of instructions, the accumulator write-back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. 2. 3. DS70165E-page 36 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 2.6.2.4 Data Space Write Saturation 2.6.3 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data space can also be saturated but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These inputs are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory. If the SATDW bit in the CORCON register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly, For input data greater than 0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. The Most Significant bit of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either of the two DSP accumulators or the X bus (to support multi-bit shifts of register or memory data). The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of `0' does not modify the operand. The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 to 31 for right shifts, and between bit positions 0 to 16 for left shifts. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 37 dsPIC33F NOTES: DS70165E-page 38 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 3.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). 3.1 Program Address Space The program address memory space of the dsPIC33F devices is 4M instructions. The space is addressable by a 24-bit value derived from either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 3.6 "Interfacing Program and Data Memory Spaces". User access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space. Memory maps for the dsPIC33F family of devices are shown in Figure 3-1. The dsPIC33F architecture features separate program and data memory spaces and buses. This architecture also allows the direct access of program memory from the data space during code execution. FIGURE 3-1: PROGRAM MEMORY MAP FOR dsPIC33F FAMILY DEVICES dsPIC33FJ64XXXXX GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table dsPIC33FJ128XXXXX GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table dsPIC33FJ256XXXXX GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table 0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200 User Memory Space User Program Flash Memory (22K instructions) User Program Flash Memory (44K instructions) User Program Flash Memory (88K instructions) 0x00ABFE 0x00AC00 0x0157FE 0x015800 Unimplemented (Read `0's) Unimplemented (Read `0's) Unimplemented (Read `0's) 0x7FFFFE 0x800000 0x02ABFE 0x02AC00 Reserved Configuration Memory Space Reserved Reserved Device Configuration Registers Device Configuration Registers Device Configuration Registers 0xF7FFFE 0xF80000 0xF80017 0xF80010 Reserved Reserved Reserved DEVID (2) DEVID (2) DEVID (2) 0xFEFFFE 0xFF0000 0xFFFFFE (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 39 dsPIC33F 3.1.1 PROGRAM MEMORY ORGANIZATION 3.1.2 INTERRUPT AND TRAP VECTORS The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 3-2). Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space. All dsPIC33F devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user at 0x000000, with the actual address for the start of code at 0x000002. dsPIC33F devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the many device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 6.1 "Interrupt Vector Table". FIGURE 3-2: msw Address 0x000001 0x000003 0x000005 0x000007 PROGRAM MEMORY ORGANIZATION most significant word 23 00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read as `0') Instruction Width 16 least significant word 8 0 0x000000 0x000002 0x000004 0x000006 PC Address (lsw Address) DS70165E-page 40 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 3.2 Data Address Space The dsPIC33F CPU has a separate 16-bit wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. Data memory maps of devices with different RAM sizes are shown in Figure 3-3 through Figure 3-5. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA<15> = 0) is used for implemented memory addresses, while the upper half (EA<15> = 1) is reserved for the Program Space Visibility area (see Section 3.6.3 "Reading Data From Program Memory Using Program Space Visibility"). dsPIC33F devices implement a total of up to 30 Kbytes of data memory. Should an EA point to a location outside of this area, an all-zero word or byte will be returned. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed but the write does not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine state prior to execution of the address Fault. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified. A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSb of any W register by executing a zero-extend (ZE) instruction on the appropriate address. 3.2.1 DATA SPACE WIDTH 3.2.3 SFR SPACE The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes of each word have even addresses, while the Most Significant Bytes have odd addresses. The first 2 Kbytes of the Near Data Space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). These are used by the dsPIC33F core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as `0'. A complete listing of implemented SFRs, including their addresses, is shown in Table 3-1 through Table 3-34. Note: The actual set of peripheral features and interrupts varies by the device. Please refer to the corresponding device tables and pinout diagrams for device-specific information. 3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC(R) devices and improve data space memory usage efficiency, the dsPIC33F instruction set supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Data byte reads will read the complete word that contains the byte, using the LSb of any EA to determine which byte to select. The selected byte is placed onto the LSb of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register which matches the byte address. 3.2.4 NEAR DATA SPACE The 8-Kbyte area between 0x0000 and 0x1FFF is referred to as the Near Data Space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a working register as an Address Pointer. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 41 dsPIC33F FIGURE 3-3: DATA MEMORY MAP FOR dsPIC33F DEVICES WITH 8 KBs RAM MSb Address MSb 2-Kbyte SFR Space 0x0001 SFR Space 0x07FF 0x0801 X Data RAM (X) 8-Kbyte SRAM Space 0x17FF 0x1801 Y Data RAM (Y) 0x1FFF 0x2001 0x27FF 0x2801 DMA RAM 0x1FFE 0x2000 0x27FE 0x2800 0x17FE 0x1800 0x07FE 0x0800 8-Kbyte Near Data Space LSb Address LSb 0x0000 16 bits 0x8001 0x8000 Optionally Mapped into Program Memory X Data Unimplemented (X) 0xFFFF 0xFFFE DS70165E-page 42 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F FIGURE 3-4: DATA MEMORY MAP FOR dsPIC33F DEVICES WITH 16 KBs RAM MSb Address MSb 2-Kbyte SFR Space 0x0001 SFR Space 0x07FF 0x0801 X Data RAM (X) 0x1FFE 0x27FE 0x2800 Y Data RAM (Y) 0x3FFF 0x4001 0x47FF 0x4801 DMA RAM 0x3FFE 0x4000 0x47FE 0x4800 0x07FE 0x0800 8-Kbyte Near Data Space LSb Address LSb 0x0000 16 bits 0x1FFF 16-Kbyte SRAM Space 0x27FF 0x2801 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 0xFFFE (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 43 dsPIC33F FIGURE 3-5: DATA MEMORY MAP FOR dsPIC33F DEVICES WITH 30 KBs RAM MSb Address MSb 2-Kbyte SFR Space 0x0001 SFR Space 0x07FF 0x0801 0x07FE 0x0800 8-Kbyte Near Data Space LSb Address LSb 0x0000 16 bits X Data RAM (X) 30-Kbyte SRAM Space 0x47FF 0x4801 Y Data RAM (Y) 0x77FF 0x7800 0x7FFF 0x8001 0x47FE 0x4800 DMA RAM 0x77FE 0x7800 0x7FFE 0x8000 Optionally Mapped into Program Memory X Data Unimplemented (X) 0xFFFF 0xFFFE DS70165E-page 44 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 3.2.5 X AND Y DATA SPACES 3.2.6 DMA RAM The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. This feature allows certain instructions to concurrently fetch two words from RAM, thereby enabling efficient execution of DSP algorithms such as Finite Impulse Response (FIR) filtering and Fast Fourier Transform (FFT). The X data space is used by all instructions and supports all addressing modes. There are separate read and write data buses for X data space. The X read data bus is the read data path for all instructions that view data space as combined X and Y address space. It is also the X data prefetch path for the dual operand DSP instructions (MAC class). The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths. Both the X and Y data spaces support Modulo Addressing mode for all instructions, subject to addressing mode restrictions. Bit-Reversed Addressing mode is only supported for writes to X data space. All data memory writes, including in DSP instructions, view data space as combined X and Y address space. The boundary between the X and Y data spaces is device-dependent and is not user-programmable. All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device. Every dsPIC33F device contains 2 Kbytes of dual ported DMA RAM located at the end of Y data space. Memory locations is part of Y data RAM and is in the DMA RAM space are accessible simultaneously by the CPU and the DMA controller module. DMA RAM is utilized by the DMA controller to store data to be transferred to various peripherals using DMA, as well as data transferred from various peripherals using DMA. The DMA RAM can be accessed by the DMA controller without having to steal cycles from the CPU. When the CPU and the DMA controller attempt to concurrently write to the same DMA RAM location, the hardware ensures that the CPU is given precedence in accessing the DMA RAM location. Therefore, the DMA RAM provides a reliable means of transferring DMA data without ever having to stall the CPU. Note: DMA RAM can be used for general purpose data storage if the DMA function is not required in an application. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 45 TABLE 3-1: SFR Name WREG0 WREG1 WREG2 WREG3 WREG4 WREG5 WREG6 WREG7 WREG8 WREG9 WREG10 WREG11 WREG12 WREG13 WREG14 WREG15 SPLIM PCL PCH TBLPAG PSVPAG RCOUNT DCOUNT DOSTARTL DOSTARTH DOENDL DOENDH SR CORCON MODCON XMODSRT XMODEND YMODSRT YMODEND XBREV DISICNT BSRAM SSRAM Legend: SFR Addr 0000 0002 0004 0006 0008 000A 000C 000E 0010 0012 0014 0016 0018 001A 001C 001E 0020 002E 0030 0032 0034 0036 0038 003A 003C 003E 0040 0042 0044 0046 0048 004A 004C 004E 0050 0052 0750 0752 CPU CORE REGISTERS MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 Program Counter High Byte Register Table Page Address Pointer Register Program Memory Visibility Page Address Pointer Register 0000 0000 0000 xxxx xxxx 0 -- -- IPL2 SATA -- -- IPL1 SATB IPL0 SATDW RA ACCSAT DOSTARTH<5:0> 0 DOENDH N IPL3 OV PSV Z RND C IF 0 1 0 1 XB<14:0> -- -- -- -- -- -- -- -- -- -- -- -- -- Disable Interrupts Counter Register -- -- -- -- -- -- -- -- -- -- -- -- IW_BSR IW_SSR IR_BSR IR_SSR RL_BSR RL_SSR xxxx 00xx xxxx 00xx 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 DS70165E-page 46 dsPIC33F Working Register 0 Working Register 1 Working Register 2 Working Register 3 Working Register 4 Working Register 5 Working Register 6 Working Register 7 Working Register 8 Working Register 9 Working Register 10 Working Register 11 Working Register 12 Working Register 13 Working Register 14 Working Register 15 Stack Pointer Limit Register Program Counter Low Word Register -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DCOUNT<15:0> DOSTARTL<15:1> -- -- OA -- XMODEN -- -- OB -- YMODEN -- -- SA -- -- -- -- SB US -- -- -- OAB EDT -- -- SAB -- -- DA DL<2:0> BWM<3:0> XS<15:1> XE<15:1> YS<15:1> YE<15:1> BREN -- -- -- -- DOENDL<15:1> -- DC Preliminary (c) 2007 Microchip Technology Inc. Repeat Loop Counter Register YWM<3:0> XWM<3:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. (c) 2007 Microchip Technology Inc. TABLE 3-2: SFR Name CNEN1 CNEN2 CNPU1 CNPU2 Legend: SFR Addr 0060 0062 0068 006A CHANGE NOTIFICATION REGISTER MAP Bit 15 CN15IE -- Bit 14 CN14IE -- Bit 13 CN13IE -- Bit 12 CN12IE -- Bit 11 CN11IE -- Bit 10 CN10IE -- Bit 9 CN9IE -- Bit 8 CN8IE -- CN8PUE -- Bit 7 CN7IE CN23IE CN7PUE Bit 6 CN6IE CN22IE CN6PUE Bit 5 CN5IE CN21IE CN5PUE Bit 4 CN4IE CN20IE CN4PUE Bit 3 CN3IE CN19IE CN3PUE Bit 2 CN2IE CN18IE CN2PUE Bit 1 CN1IE CN17IE CN1PUE Bit 0 CN0IE CN16IE CN0PUE All Resets 0000 0000 0000 0000 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE -- -- -- -- -- -- -- CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Preliminary dsPIC33F DS70165E-page 47 DS70165E-page 48 dsPIC33F TABLE 3-3: SFR Name INTCON1 INTCON2 IFS0 IFS1 IFS2 IFS3 IFS4 IEC0 IEC1 IEC2 IEC3 IEC4 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC10 IPC11 IPC12 IPC13 IPC14 IPC15 IPC16 IPC17 Legend: SFR Addr 0080 0082 0084 0086 0088 008A 008C 0094 0096 0098 009A 009C 00A4 00A6 00A8 00AA 00AC 00AE 00B0 00B2 00B4 00B6 00B8 00BA 00BC 00BE 00C0 00C2 00C4 00C6 INTERRUPT CONTROLLER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 OVBTE -- Bit 8 COVTE -- T3IF DMA2IF IC6IF C2IF -- T3IE DMA2IE IC6IE C2IE -- Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 OSCFAIL INT1EP IC1IF MI2C1IF SPI2IF SI2C2IF U1EIF IC1IE Bit 0 -- INT0EP INT0IF SI2C1IF SPI2EIF T7IF FLTBIF INT0IE All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE ALTIVT -- U2TXIF T6IF FLTAIF -- -- U2TXIE T6IE FLTAIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DISI DMA1IF U2RXIF DMA4IF -- -- DMA1IE U2RXIE DMA4IE -- -- -- AD1IF INT2IF -- DMA5IF -- AD1IE INT2IE -- DMA5IE -- T1IP<2:0> T2IP<2:0> U1RXIP<2:0> -- CNIP<2:0> IC8IP<2:0> T4IP<2:0> U2TXIP<2:0> C1IP<2:0> IC5IP<2:0> OC7IP<2:0> T6IP<2:0> T8IP<2:0> C2RXIP<2:0> DCIEIP<2:0> FLTAIP<2:0> -- C2TXIP<2:0> -- -- -- U1TXIF T5IF OC8IF DCIIF -- U1TXIE T5IE OC8IE DCIIE -- -- U1RXIF T4IF OC7IF DCIEIF -- U1RXIE T4IE OC7IE DCIEIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR -- T2IF IC8IF IC5IF C2RXIF C2TXIF T2IE IC8IE IC5IE C2RXIE C2TXIE -- -- -- -- -- OC2IF IC7IF IC4IF INT4IF C1TXIF OC2IE IC7IE IC4IE INT4IE C1TXIE -- IC2IF AD2IF IC3IF INT3IF DMA7IF IC2IE AD2IE IC3IE INT3IE DMA7IE IC1IP<2:0> IC2IP<2:0> SPI1EIP<2:0> AD1IP<2:0> MI2C1IP<2:0> AD2IP<2:0> OC3IP<2:0> INT2IP<2:0> SPI2IP<2:0> IC3IP<2:0> OC5IP<2:0> -- -- SI2C2IP<2:0> INT3IP<2:0> PWMIP<2:0> DMA5IP<2:0> U1EIP<2:0> DMA7IP<2:0> -- INT4EP DMA0IF INT1IF DMA3IF T9IF DMA6IF DMA0IE INT1IE DMA3IE T9IE DMA6IE INT3EP T1IF CNIF C1IF T8IF -- T1IE CNIE C1IE T8IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INT2EP OC1IF -- C1RXIF MI2C2IF U2EIF OC1IE -- C1RXIE MI2C2IE U2EIE SPI1IF SPI1EIF OC4IF OC6IF QEIIF -- OC3IF OC5IF PWMIF -- SPI1IE SPI1EIE OC4IE OC6IE QEIIE -- OC3IE OC5IE PWMIE -- OC1IP<2:0> OC2IP<2:0> SPI1IP<2:0> DMA1IP<2:0> -- IC7IP<2:0> OC4IP<2:0> U2RXIP<2:0> C1RXIP<2:0> IC4IP<2:0> OC6IP<2:0> DMA4IP<2:0> MI2C2IP<2:0> INT4IP<2:0> QEIIP<2:0> -- U2EIP<2:0> C1TXIP<2:0> MI2C1IE SI2C1IE SPI2IE SI2C2IE U1EIE INT0IP<2:0> DMA0IP<2:0> T3IP<2:0> U1TXIP<2:0> SI2C1IP<2:0> INT1IP<2:0> DMA2IP<2:0> T5IP<2:0> SPI2EIP<2:0> DMA3IP<2:0> IC6IP<2:0> OC8IP<2:0> T7IP<2:0> T9IP<2:0> C2IP<2:0> DCIIP<2:0> FLTBIP<2:0> DMA6IP<2:0> SPI2EIE T7IE FLTBIE Preliminary (c) 2007 Microchip Technology Inc. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 3-4: SFR Name TMR1 PR1 T1CON TMR2 SFR Addr 0100 0102 0104 0106 TIMER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx FFFF TGATE TCKPS<1:0> -- TSYNC TCS -- 0000 xxxx xxxx xxxx FFFF FFFF TGATE TGATE TCKPS<1:0> TCKPS<1:0> T32 -- -- -- TCS TCS -- -- 0000 0000 xxxx xxxx xxxx FFFF FFFF TGATE TGATE TCKPS<1:0> TCKPS<1:0> T32 -- -- -- TCS TCS -- -- 0000 0000 xxxx xxxx xxxx FFFF FFFF TGATE TGATE TCKPS<1:0> TCKPS<1:0> T32 -- -- -- TCS TCS -- -- 0000 0000 xxxx xxxx xxxx FFFF FFFF TGATE TGATE TCKPS<1:0> TCKPS<1:0> T32 -- -- -- TCS TCS -- -- 0000 0000 (c) 2007 Microchip Technology Inc. Timer1 Register Period Register 1 TON -- TSIDL -- -- -- -- -- -- Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Period Register 2 Period Register 3 TON TON -- -- TSIDL TSIDL -- -- -- -- -- -- -- -- -- -- -- -- TMR3HLD 0108 TMR3 PR2 PR3 T2CON T3CON TMR4 TMR5HLD TMR5 PR4 010A 010C 010E 0110 0112 0114 0116 0118 011A 011C 011E 0120 0122 TON TON -- -- TSIDL TSIDL -- -- -- -- -- -- Timer4 Register Timer5 Holding Register (for 32-bit operations only) Timer5 Register Period Register 4 Period Register 5 -- -- -- -- -- -- Preliminary DS70165E-page 49 PR5 T4CON T5CON TMR6 Timer6 Register Timer7 Holding Register (for 32-bit operations only) Timer7 Register Period Register 6 Period Register 7 TON TON -- -- TSIDL TSIDL -- -- -- -- -- -- -- -- -- -- -- -- TMR7HLD 0124 TMR7 PR6 PR7 T6CON T7CON TMR8 0126 0128 012A 012C 012E 0130 Timer8 Register Timer9 Holding Register (for 32-bit operations only) Timer9 Register Period Register 8 Period Register 9 TON TON -- -- TSIDL TSIDL -- -- -- -- -- -- -- -- -- -- -- -- TMR9HLD 0132 TMR9 PR8 PR9 T8CON T9CON Legend: 0134 0136 0138 013A 013C dsPIC33F x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DS70165E-page 50 dsPIC33F TABLE 3-5: SFR Name IC1BUF IC1CON IC2BUF IC2CON IC3BUF IC3CON IC4BUF IC4CON IC5BUF IC5CON IC6BUF IC6CON IC7BUF IC7CON IC8BUF IC8CON Legend: SFR Addr 0140 0142 0144 0146 0148 014A 014C 014E 0150 0152 0154 0156 0158 015A 015C 015E INPUT CAPTURE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx ICI<1:0> ICOV ICBNE ICM<2:0> 0000 xxxx ICI<1:0> ICOV ICBNE ICM<2:0> 0000 xxxx ICI<1:0> ICOV ICBNE ICM<2:0> 0000 xxxx ICI<1:0> ICOV ICBNE ICM<2:0> 0000 xxxx ICI<1:0> ICOV ICBNE ICM<2:0> 0000 xxxx ICI<1:0> ICOV ICBNE ICM<2:0> 0000 xxxx ICI<1:0> ICOV ICBNE ICM<2:0> 0000 xxxx ICI<1:0> ICOV ICBNE ICM<2:0> 0000 Input 1 Capture Register -- -- ICSIDL -- -- -- -- -- ICTMR Input 2 Capture Register -- -- ICSIDL -- -- -- -- -- ICTMR Input 3 Capture Register -- -- ICSIDL -- -- -- -- -- ICTMR Input 4 Capture Register -- -- ICSIDL -- -- -- -- -- ICTMR Input 5 Capture Register -- -- ICSIDL -- -- -- -- -- ICTMR Input 6 Capture Register -- -- ICSIDL -- -- -- -- -- ICTMR Input 7 Capture Register -- -- ICSIDL -- -- -- -- -- ICTMR Preliminary (c) 2007 Microchip Technology Inc. Input 8 Capture Register -- -- ICSIDL -- -- -- -- -- ICTMR x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. (c) 2007 Microchip Technology Inc. TABLE 3-6: SFR Name OC1RS OC1R OC1CON OC2RS OC2R OC2CON OC3RS OC3R OC3CON OC4RS OC4R OC4CON OC5RS OC5R OC5CON OC6RS OC6R OC6CON OC7RS OC7R OC7CON OC8RS OC8R OC8CON Legend: SFR Addr 0180 0182 0184 0186 0188 018A 018C 018E 0190 0192 0194 0196 0198 019A 019C 019E 01A0 01A2 01A4 01A6 01A8 01AA 01AC 01AE OUTPUT COMPARE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx -- OCFLT OCTSEL OCM<2:0> 0000 xxxx xxxx -- OCFLT OCTSEL OCM<2:0> 0000 xxxx xxxx -- OCFLT OCTSEL OCM<2:0> 0000 xxxx xxxx -- OCFLT OCTSEL OCM<2:0> 0000 xxxx xxxx -- OCFLT OCTSEL OCM<2:0> 0000 xxxx xxxx -- OCFLT OCTSEL OCM<2:0> 0000 xxxx xxxx -- OCFLT OCTSEL OCM<2:0> 0000 xxxx xxxx -- OCFLT OCTSEL OCM<2:0> 0000 Output Compare 1 Secondary Register Output Compare 1 Register -- -- OCSIDL -- -- -- -- -- -- -- Output Compare 2 Secondary Register Output Compare 2 Register -- -- OCSIDL -- -- -- -- -- -- -- Output Compare 3 Secondary Register Output Compare 3 Register -- -- OCSIDL -- -- -- -- -- -- -- Output Compare 4 Secondary Register Output Compare 4 Register -- -- OCSIDL -- -- -- -- -- -- -- Output Compare 5 Secondary Register Output Compare 5 Register -- -- OCSIDL -- -- -- -- -- -- -- Preliminary DS70165E-page 51 Output Compare 6 Secondary Register Output Compare 6 Register -- -- OCSIDL -- -- -- -- -- -- -- Output Compare 7 Secondary Register Output Compare 7 Register -- -- OCSIDL -- -- -- -- -- -- -- Output Compare 8 Secondary Register Output Compare 8 Register -- -- OCSIDL -- -- -- -- -- -- -- x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. dsPIC33F DS70165E-page 52 dsPIC33F TABLE 3-7: SFR Name Addr. PTCON PTMR PTPER SEVTCMP 01C0 01C2 01C4 01C6 8-OUTPUT PWM REGISTER MAP Bit 15 PTEN PTDIR -- SEVTDI R -- -- -- -- -- -- -- -- PMOD4 PMOD3 Bit 14 -- Bit 13 PTSIDL Bit 12 -- Bit 11 -- Bit 10 -- Bit 9 -- Bit 8 -- Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PEN1H -- PEN4L -- PEN3L IUE PEN2L OSYNC PEN1L UDIS 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 DTS1A FAEN2 FBEN2 POUT1 H DTS1I FAEN1 FBEN1 POUT1 L 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0> PWM Timer Count Value Register PWM Time Base Period Register PWM Special Event Compare Register PMOD2 PMOD1 PEN4H -- PEN3H -- PEN2H -- PWMCON1 01C8 PWMCON2 01CA DTCON1 DTCON2 FLTACON FLTBCON OVDCON PDC1 PDC2 PDC3 PDC4 Legend: 01CC 01CE 01D0 01D2 SEVOPS<3:0> DTB<5:0> DTBPS<1:0> -- -- -- FAOV3 H FBOV3 H POVD3 H -- FAOV3L FBOV3L POVD3 L DTAPS<1:0> -- FAOV1 H FBOV1 H POVD1 H -- FAOV1L FBOV1L POVD1L DTS4A FLTAM FLTBM POUT4 H DTS4I -- -- POUT4 L DTS3A -- -- POUT3 H DTS3I -- -- POUT3 L DTA<5:0> DTS2A FAEN4 FBEN4 POUT2 H DTS2I FAEN3 FBEN3 POUT2 L -- FAOV2 H FBOV2 H POVD2 H -- FAOV2L FBOV2L POVD2L FAOV4H FAOV4L FBOV4H FBOV4L POVD4 L 01D4 POVD4H 01D6 01D8 01DA 01DC PWM Duty Cycle #1 Register PWM Duty Cycle #2 Register PWM Duty Cycle #3 Register PWM Duty Cycle #4 Register Preliminary (c) 2007 Microchip Technology Inc. u = uninitialized bit, -- = unimplemented, read as `0' TABLE 3-8: SFR Name QEICON DFLTCON POSCNT MAXCNT Legend: Addr . QEI REGISTER MAP Bit 15 Bit 14 -- -- Bit 13 QEISIDL -- Bit 12 Bit 11 INDX -- UPDN -- Bit 10 Bit 9 Bit 8 Bit 7 SWPAB CEID QEOUT Bit 6 PCDOUT Bit 5 TQGATE QECK<2:0> Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 (c) 2007 Microchip Technology Inc. 01E0 CNTERR 01E2 01E4 01E6 -- QEIM<2:0> IMV<1:0> TQCKPS<1:0> -- POSRES TQCS UPDN_SRC -- -- -- Position Counter<15:0> Maximum Count<15:0> u = uninitialized bit, -- = unimplemented, read as `0' TABLE 3-9: SFR Name I2C1RCV I2C1TRN I2C1BRG I2C1CON I2C1STAT SFR Addr 0200 0202 0204 0206 0208 020A 020C I2C1 REGISTER MAP Bit 15 -- -- -- I2CEN ACKSTAT -- -- Bit 14 -- -- -- -- TRSTAT -- -- Bit 13 -- -- -- I2CSIDL -- -- -- Bit 12 -- -- -- SCLREL -- -- -- Bit 11 -- -- -- IPMIEN -- -- -- Bit 10 -- -- -- A10M BCL -- -- Bit 9 -- -- -- DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV Bit 8 -- -- Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 00FF 0000 PEN R_W RSEN RBF SEN TBF 1000 0000 0000 0000 Receive Register Transmit Register Baud Rate Generator Register ACKDT D_A ACKEN P RCEN S Preliminary DS70165E-page 53 I2C1ADD I2C1MSK Legend: Address Register Address Mask Register x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 3-10: SFR Name I2C2RCV I2C2TRN I2C2BRG I2C2CON I2C2STAT I2C2ADD I2C2MSK Legend: SFR Addr 0210 0212 0214 0216 0218 021A 021C I2C2 REGISTER MAP Bit 15 -- -- -- I2CEN ACKSTAT -- -- Bit 14 -- -- -- -- TRSTAT -- -- Bit 13 -- -- -- I2CSIDL -- -- -- Bit 12 -- -- -- SCLREL -- -- -- Bit 11 -- -- -- IPMIEN -- -- -- Bit 10 -- -- -- A10M BCL -- -- Bit 9 -- -- -- DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV Bit 8 -- -- Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 00FF 0000 PEN R_W RSEN RBF SEN TBF 1000 0000 0000 0000 Receive Register Transmit Register Baud Rate Generator Register ACKDT D_A ACKEN P RCEN S Address Register Address Mask Register dsPIC33F x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DS70165E-page 54 dsPIC33F TABLE 3-11: SFR Name U1MODE U1STA U1TXREG U1RXREG U1BRG Legend: SFR Addr 0220 0222 0224 0226 0228 UART1 REGISTER MAP Bit 15 UARTEN UTXISEL1 -- -- Bit 14 -- Bit 13 USIDL Bit 12 IREN -- -- -- Bit 11 RTSMD UTXBRK -- -- Bit 10 -- UTXEN -- -- Bit 9 UEN1 UTXBF -- -- Baud Rate Generator Prescaler Bit 8 UEN0 TRMT Bit 7 WAKE Bit 6 LPBACK Bit 5 ABAUD ADDEN Bit 4 URXINV RIDLE Bit 3 BRGH PERR Bit 2 Bit 1 Bit 0 STSEL URXDA All Resets 0000 0110 xxxx 0000 0000 PDSEL<1:0> FERR OERR UTXINV UTXISEL0 -- -- -- -- URXISEL<1:0> UART Transmit Register UART Receive Register x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 3-12: SFR Name U2MODE U2STA U2TXREG U2RXREG U2BRG Legend: SFR Addr 0230 0232 0234 0236 0238 UART2 REGISTER MAP Bit 15 UARTEN UTXISEL1 -- -- Bit 14 -- UTXINV -- -- Bit 13 USIDL UTXISEL0 -- -- Bit 12 IREN -- -- -- Bit 11 RTSMD UTXBRK -- -- Bit 10 -- UTXEN -- -- Bit 9 UEN1 UTXBF -- -- Baud Rate Generator Prescaler Bit 8 UEN0 TRMT Bit 7 WAKE Bit 6 LPBACK Bit 5 ABAUD ADDEN Bit 4 URXINV RIDLE Bit 3 BRGH PERR Bit 2 Bit 1 Bit 0 STSEL URXDA All Resets 0000 0110 xxxx 0000 0000 PDSEL<1:0> FERR OERR URXISEL<1:0> UART Transmit Register UART Receive Register Preliminary (c) 2007 Microchip Technology Inc. x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 3-13: SFR Name SPI1STAT SPI1CON1 SPI1CON2 SPI1BUF Legend: SFR Addr 0240 0242 0244 0248 SPI1 REGISTER MAP Bit 15 SPIEN -- FRMEN Bit 14 -- -- SPIFSD Bit 13 SPISIDL -- FRMPOL Bit 12 -- DISSCK -- Bit 11 -- DISSDO -- Bit 10 -- MODE16 -- Bit 9 -- SMP -- Bit 8 -- CKE -- Bit 7 -- SSEN -- Bit 6 SPIROV CKP -- Bit 5 -- MSTEN -- -- Bit 4 -- Bit 3 -- SPRE<2:0> -- -- Bit 2 -- Bit 1 SPITBF Bit 0 SPIRBF All Resets 0000 0000 0000 0000 PPRE<1:0> FRMDLY -- SPI1 Transmit and Receive Buffer Register x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 3-14: SFR Name SPI2STAT SPI2CON1 SPI2CON2 SPI2BUF Legend: SFR Addr 0260 0262 0264 0268 SPI2 REGISTER MAP Bit 15 SPIEN -- FRMEN Bit 14 -- -- SPIFSD Bit 13 SPISIDL -- FRMPOL Bit 12 -- DISSCK -- Bit 11 -- DISSDO -- Bit 10 -- MODE16 -- Bit 9 -- SMP -- Bit 8 -- CKE -- Bit 7 -- SSEN -- Bit 6 SPIROV CKP -- Bit 5 -- MSTEN -- -- Bit 4 -- Bit 3 -- SPRE<2:0> -- -- Bit 2 -- Bit 1 SPITBF Bit 0 SPIRBF All Resets 0000 0000 0000 0000 PPRE<1:0> FRMDLY -- SPI2 Transmit and Receive Buffer Register x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 3-15: File Name ADC1BUF0 AD1CON1 AD1CON2 AD1CON3 AD1CHS123 AD1CHS0 AD1PCFGH AD1PCFGL AD1CSSH AD1CSSL AD1CON4 Legend: Addr 0300 0320 0322 0324 0326 0328 032A 032C 032E 0330 0332 ADC1 REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx SSRC<2:0> BUFS -- CH123SB -- CH0NA PCFG24 PCFG8 CSS24 CSS8 -- PCFG23 PCFG7 CSS23 CSS7 -- -- -- -- -- PCFG22 PCFG6 CSS22 CSS6 -- -- -- PCFG21 PCFG5 CSS21 CSS5 -- PCFG20 PCFG4 CSS20 CSS4 -- -- -- SIMSAM ASAM SAMP BUFM DONE ALTS 0000 0000 0000 CH123SA 0000 0000 PCFG16 PCFG0 CSS16 CSS0 0000 0000 0000 0000 0000 (c) 2007 Microchip Technology Inc. ADC Data Buffer 0 ADON -- VCFG<2:0> ADRC -- CH0NB -- -- -- -- -- -- PCFG29 PCFG13 CSS29 CSS13 -- PCFG28 PCFG12 CSS28 CSS12 -- -- -- ADSIDL ADDMABM -- -- -- AD12B CSCNA SAMC<4:0> CH123NB<1:0> CH0SB<4:0> PCFG27 PCFG26 PCFG25 PCFG11 PCFG10 CSS27 CSS11 -- CSS26 CSS10 -- PCFG9 CSS25 CSS9 -- FORM<1:0> CHPS<1:0> SMPI<3:0> ADCS<5:0> -- CH123NA<1:0> CH0SA<4:0> PCFG31 PCFG30 PCFG15 PCFG14 CSS31 CSS15 -- CSS30 CSS14 -- PCFG19 PCFG18 PCFG17 PCFG3 CSS19 CSS3 -- PCFG2 CSS18 CSS2 PCFG1 CSS17 CSS1 DMABL<2:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 3-16: ADC2 REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx SSRC<2:0> BUFS -- CH123SB -- CH0NA -- PCFG8 -- CSS8 -- -- PCFG7 -- CSS7 -- -- -- -- -- -- PCFG6 -- CSS6 -- -- -- -- PCFG5 -- CSS5 -- -- -- -- PCFG4 -- CSS4 -- -- PCFG3 -- CSS3 -- -- SIMSAM ASAM SAMP BUFM DONE ALTS 0000 0000 0000 CH123SA 0000 0000 -- PCFG0 -- CSS0 0000 0000 0000 0000 0000 Preliminary DS70165E-page 55 File Name ADC2BUF0 AD2CON1 AD2CON2 AD2CON3 AD2CHS123 AD2CHS0 Reserved AD2PCFGL Reserved AD2CSSL AD2CON4 Legend: Addr 0340 0360 0362 0364 0366 0368 036A 036C 036E 0370 0372 ADC Data Buffer 0 ADON -- VCFG<2:0> ADRC -- CH0NB -- -- -- -- -- -- -- -- -- PCFG13 -- CSS13 -- -- -- -- PCFG12 -- CSS12 -- -- -- ADSIDL ADDMABM -- -- -- AD12B CSCNA SAMC<4:0> CH123NB<1:0> CH0SB<3:0> -- -- PCFG9 -- CSS9 -- FORM<1:0> CHPS<1:0> SMPI<3:0> ADCS<5:0> -- CH123NA<1:0> CH0SA<3:0> -- PCFG2 -- CSS2 -- PCFG1 -- CSS1 PCFG15 PCFG14 -- CSS15 -- -- CSS14 -- PCFG11 PCFG10 -- CSS11 -- -- CSS10 -- DMABL<2:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. dsPIC33F TABLE 3-17: File Name Addr DMA0CON 0380 DMA0REQ 0382 DMA0STA DMA0STB DMA0PAD DMA0CNT 0384 0386 0388 038A DMA REGISTER MAP Bit 15 CHEN FORCE Bit 14 SIZE -- Bit 13 DIR -- Bit 12 HALF -- Bit 11 NULLW -- Bit 10 -- -- Bit 9 -- -- Bit 8 -- -- Bit 7 -- -- STA<15:0> STB<15:0> PAD<15:0> -- CHEN FORCE -- SIZE -- -- DIR -- -- HALF -- -- NULLW -- -- -- -- -- -- -- -- -- -- STA<15:0> STB<15:0> PAD<15:0> -- CHEN FORCE -- SIZE -- -- DIR -- -- HALF -- -- NULLW -- -- -- -- -- -- -- -- -- -- STA<15:0> STB<15:0> PAD<15:0> -- CHEN FORCE -- SIZE -- -- DIR -- -- HALF -- -- NULLW -- -- -- -- -- -- -- -- -- -- STA<15:0> STB<15:0> PAD<15:0> -- CHEN FORCE -- SIZE -- -- DIR -- -- HALF -- -- NULLW -- -- -- -- -- -- -- -- -- -- STA<15:0> STB<15:0> PAD<15:0> -- CHEN FORCE -- SIZE -- -- DIR -- -- HALF -- -- NULLW -- -- -- -- -- -- -- -- -- -- STA<15:0> STB<15:0> PAD<15:0> -- CNT<9:0> AMODE<1:0> -- IRQSEL<6:0> -- MODE<1:0> -- CNT<9:0> AMODE<1:0> -- IRQSEL<6:0> -- MODE<1:0> -- CNT<9:0> AMODE<1:0> -- IRQSEL<6:0> -- MODE<1:0> -- CNT<9:0> AMODE<1:0> -- IRQSEL<6:0> -- MODE<1:0> -- CNT<9:0> AMODE<1:0> -- IRQSEL<6:0> -- MODE<1:0> Bit 6 -- Bit 5 Bit 4 Bit 3 -- IRQSEL<6:0> Bit 2 -- Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 DS70165E-page 56 dsPIC33F AMODE<1:0> MODE<1:0> DMA1CON 038C DMA1REQ 038E DMA1STA DMA1STB DMA1PAD DMA1CNT 0390 0392 0394 0396 DMA2CON 0398 DMA2REQ 039A Preliminary (c) 2007 Microchip Technology Inc. DMA2STA DMA2STB DMA2PAD DMA2CNT 039C 039E 03A0 03A2 DMA3CON 03A4 DMA3REQ 03A6 DMA3STA DMA3STB 03A8 03AA DMA3PAD 03AC DMA3CNT 03AE DMA4CON 03B0 DMA4REQ 03B2 DMA4STA DMA4STB DMA4PAD 03B4 03B6 03B8 DMA4CNT 03BA DMA5CON 03BC DMA5REQ 03BE DMA5STA DMA5STB DMA5PAD Legend: 03C0 03C2 03C4 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. (c) 2007 Microchip Technology Inc. TABLE 3-17: File Name Addr DMA5CNT 03C6 DMA6CON 03C8 DMA REGISTER MAP (CONTINUED) Bit 15 -- CHEN Bit 14 -- SIZE -- Bit 13 -- DIR -- Bit 12 -- HALF -- Bit 11 -- NULLW -- Bit 10 -- -- -- -- -- -- -- -- -- STA<15:0> STB<15:0> PAD<15:0> -- CHEN FORCE -- SIZE -- -- DIR -- -- HALF -- -- NULLW -- -- -- -- -- -- -- -- -- -- STA<15:0> STB<15:0> PAD<15:0> -- -- -- -- -- -- XWCOL7 PPST7 DSADR<15:0> CNT<9:0> XWCOL6 XWCOL5 PPST6 PPST5 XWCOL4 PPST4 XWCOL3 PPST3 XWCOL2 PPST2 XWCOL1 XWCOL0 PPST1 PPST0 -- CNT<9:0> AMODE<1:0> -- IRQSEL<6:0> -- MODE<1:0> -- Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 -- IRQSEL<6:0> -- MODE<1:0> 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CNT<9:0> AMODE<1:0> DMA6REQ 03CA FORCE DMA6STA DMA6STB DMA6PAD 03CC 03CE 03D0 DMA6CNT 03D2 DMA7CON 03D4 DMA7REQ 03D6 DMA7STA DMA7STB 03D8 03DA DMA7PAD 03DC DMA7CNT 03DE DMACS0 DMACS1 DSADR Legend: 03E0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 03E2 03E4 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. -- -- -- -- LSTCH<3:0> Preliminary DS70165E-page 57 dsPIC33F DS70165E-page 58 dsPIC33F TABLE 3-18: File Name C1CTRL1 C1CTRL2 C1VEC C1FCTRL C1FIFO C1INTF C1INTE C1EC C1CFG1 C1CFG2 C1FEN1 ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 OR 1 Bit 15 -- -- -- Bit 14 -- -- -- DMABS<2:0> -- -- -- -- -- -- TXBO -- TXBP -- Bit 13 CSIDL -- -- -- -- FBP<5:0> RXBP -- TXWAR -- RXWAR -- EWARN -- Bit 12 ABAT -- Bit 11 CANCK S -- -- FILHIT<4:0> -- -- -- Bit 10 Bit 9 REQOP<2:0> -- -- -- -- -- -- IVRIF IVRIE -- -- WAKIF WAKIE ERRIF ERRIE -- -- -- Bit 8 Bit 7 Bit 6 OPMODE<2:0> -- -- Bit 5 Bit 4 -- Bit 3 CANCAP Bit 2 -- Bit 1 -- Bit 0 WIN All Reset s 0480 0000 0000 0000 0000 RBIF RBIE TBIF TBIE 0000 0000 0000 0000 PRSEG<2:0> FLTEN2 FLTEN1 FLTEN0 0000 0000 0000 0000 Addr 0400 0402 0404 0406 0408 040A 040C 040E 0410 0412 0414 0418 041A DNCNT<4:0> ICODE<6:0> FSA<4:0> FNRB<5:0> FIFOIF FIFOIE RBOVIF RBOVIE TERRCNT<7:0> -- -- FLTEN15 -- WAKFIL FLTEN14 -- -- FLTEN13 -- -- FLTEN12 -- -- FLTEN11 -- -- SEG2PH<2:0> FLTEN10 FLTEN9 FLTEN8 -- SJW<1:0> SEG2PHT S FLTEN7 SAM FLTEN6 RERRCNT<7:0> BRP<5:0> SEG1PH<2:0> FLTEN5 FLTEN4 FLTEN3 Preliminary (c) 2007 Microchip Technology Inc. C1FMSKSEL1 C1FMSKSEL2 Legend: F7MSK<1:0> F15MSK<1:0> F6MSK<1:0> F14MSK<1:0> F5MSK<1:0> F13MSK<1:0> F4MSK<1:0> F12MSK<1:0> F3MSK<1:0> F11MSK<1:0> F2MSK<1:0> F10MSK<1:0> F1MSK<1:0> F9MSK<1:0> F0MSK<1:0> F8MSK<1:0> -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 3-19: File Name Addr 0400041E C1RXFUL1 C1RXFUL2 C1RXOVF1 C1RXOVF2 ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets See definition when WIN = x RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx 0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 TXEN1 TXEN3 TXEN5 TXEN7 TXABT1 TXABT3 TXABT5 TXABT7 TXLARB1 TXLARB3 TXLARB5 TXLARB7 TXERR1 TXERR3 TXERR5 TXERR7 TXREQ1 TXREQ3 TXREQ5 TXREQ7 RTREN1 RTREN3 RTREN5 RTREN7 TX1PRI<1:0> TX3PRI<1:0> TX5PRI<1:0> TX7PRI<1:0> TXEN0 TXEN2 TXEN4 TXEN6 TXABAT0 TXLARB0 TXABAT2 TXLARB2 TXABAT4 TXLARB4 TXABAT6 TXLARB6 TXERR0 TXERR2 TXERR4 TXERR6 TXREQ0 TXREQ2 TXREQ4 TXREQ6 RTREN0 RTREN2 RTREN4 RTREN6 TX0PRI<1:0> TX2PRI<1:0> TX4PRI<1:0> TX6PRI<1:0> C1TR01CON 0430 C1TR23CON 0432 C1TR45CON 0434 C1TR67CON 0436 C1RXD C1TXD Legend: 0440 0442 Received Data Word Transmit Data Word x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. (c) 2007 Microchip Technology Inc. TABLE 3-20: File Name ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets Addr 0400041E See definition when WIN = x F3BP<3:0> F7BP<3:0> F11BP<3:0> F15BP<3:0> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> F2BP<3:0> F6BP<3:0> F10BP<3:0> F14BP<3:0> F1BP<3:0> F5BP<3:0> F9BP<3:0> F13BP<3:0> SID<2:0> -- MIDE F0BP<3:0> F4BP<3:0> F8BP<3:0> F12BP<3:0> -- EID<17:16> 0000 0000 0000 0000 xxxx xxxx -- EID<17:16> xxxx xxxx -- EID<17:16> xxxx xxxx -- EID<17:16> xxxx xxxx -- EID<17:16> xxxx xxxx -- EID<17:16> xxxx xxxx -- EID<17:16> xxxx xxxx -- EID<17:16> xxxx xxxx -- EID<17:16> xxxx xxxx -- EID<17:16> xxxx xxxx -- EID<17:16> xxxx xxxx -- EID<17:16> xxxx xxxx -- EID<17:16> xxxx xxxx -- EID<17:16> xxxx xxxx C1BUFPNT1 C1BUFPNT2 C1BUFPNT3 C1BUFPNT4 C1RXM0SID C1RXM0EID C1RXM1SID C1RXM1EID C1RXM2SID C1RXM2EID C1RXF0SID C1RXF0EID C1RXF1SID C1RXF1EID C1RXF2SID C1RXF2EID C1RXF3SID C1RXF3EID C1RXF4SID C1RXF4EID C1RXF5SID C1RXF5EID C1RXF6SID C1RXF6EID C1RXF7SID C1RXF7EID C1RXF8SID C1RXF8EID 0420 0422 0424 0426 0430 0432 0434 0436 0438 043A 0440 0442 0444 0446 0448 044A 044C 044E 0450 0452 0454 0456 0458 045A 045C 045E 0460 0462 0464 0466 0468 046A EID<7:0> -- MIDE EID<7:0> -- MIDE EID<7:0> -- EXIDE EID<7:0> -- EXIDE Preliminary DS70165E-page 59 EID<7:0> -- EXIDE EID<7:0> -- EXIDE EID<7:0> -- EXIDE EID<7:0> -- EXIDE EID<7:0> -- EXIDE EID<7:0> -- EXIDE EID<7:0> -- EXIDE dsPIC33F EID<7:0> -- EXIDE C1RXF9SID C1RXF9EID C1RXF10SID C1RXF10EID Legend: EID<7:0> -- EXIDE EID<7:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 3-20: File Name C1RXF11SID C1RXF11EID C1RXF12SID C1RXF12EID C1RXF13SID C1RXF13EID C1RXF14SID C1RXF14EID C1RXF15SID C1RXF15EID Legend: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (CONTINUED) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 SID<2:0> Bit 5 Bit 4 -- Bit 3 EXIDE Bit 2 -- Bit 1 Bit 0 All Resets xxxx xxxx -- EID<17:16> xxxx xxxx -- EID<17:16> xxxx xxxx -- EID<17:16> xxxx xxxx -- EID<17:16> xxxx xxxx DS70165E-page 60 dsPIC33F Addr 046C 046E 0470 0472 0474 0476 0478 047A 047C 047E SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> EID<17:16> EID<7:0> SID<2:0> -- EXIDE EID<7:0> SID<2:0> -- EXIDE EID<7:0> SID<2:0> -- EXIDE EID<7:0> SID<2:0> -- EXIDE EID<7:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Preliminary (c) 2007 Microchip Technology Inc. (c) 2007 Microchip Technology Inc. TABLE 3-21: File Name C2CTRL1 C2CTRL2 C2VEC C2FCTRL C2FIFO C2INTF C2INTE C2EC C2CFG1 C2CFG2 C2FEN1 C2FMSKSEL1 C2FMSKSEL2 Legend: Addr 0500 0502 0504 0506 0508 050A ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0 OR 1 Bit 15 -- -- -- Bit 14 -- -- -- DMABS<2:0> -- -- -- -- -- -- TXBO -- TXBP -- Bit 13 CSIDL -- -- -- -- FBP<5:0> RXBP -- TXWAR -- RXWAR EWARN -- -- Bit 12 ABAT -- Bit 11 CANCKS -- -- FILHIT<4:0> -- -- -- Bit 10 Bit 9 REQOP<2:0> -- -- -- -- -- -- IVRIF IVRIE -- -- WAKIF WAKIE ERRIF ERRIE -- -- -- Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 -- -- Bit 3 CANCAP Bit 2 -- Bit 1 -- Bit 0 WIN All Resets 0480 0000 0000 0000 0000 RBIF RBIE TBIF TBIE 0000 0000 0000 0000 PRSEG<2:0> FLTEN2 FLTEN1 FLTEN0 0000 0000 0000 0000 OPMODE<2:0> -- DNCNT<4:0> ICODE<6:0> FSA<4:0> FNRB<5:0> FIFOIF FIFOIE RBOVIF RBOVIE 050C 050E 0510 0512 0514 0518 051A TERRCNT<7:0> -- -- FLTEN15 -- WAKFIL FLTEN14 -- -- FLTEN13 -- -- FLTEN12 -- -- FLTEN11 -- -- SEG2PH<2:0> FLTEN10 FLTEN9 FLTEN8 F4MSK<1:0> F12MSK<1:0> -- SJW<1:0> SEG2PHTS FLTEN7 SAM RERRCNT<7:0> BRP<5:0> SEG1PH<2:0> FLTEN6 FLTEN5 FLTEN4 FLTEN3 F2MSK<1:0> F10MSK<1:0> F7MSK<1:0> F15MSK<1:0> F6MSK<1:0> F14MSK<1:0> F5MSK<1:0> F13MSK<1:0> F3MSK<1:0> F11MSK<1:0> F1MSK<1:0> F9MSK<1:0> F0MSK<1:0> F8MSK<1:0> -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Preliminary DS70165E-page 61 TABLE 3-22: File Name Addr 0500051E C2RXFUL1 C2RXFUL2 C2RXOVF1 C2RXOVF2 ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets See definition when WIN = x RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000 0000 0000 0000 0000 0000 0520 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 0522 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0528 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF09 RXOVF08 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 052A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 TXEN1 TXEN3 TXEN5 TXEN7 TX ABAT1 TX ABAT3 TX ABAT5 TX ABAT7 TX LARB1 TX LARB3 TX LARB5 TX LARB7 TX ERR1 TX ERR3 TX ERR5 TX ERR7 TX REQ1 TX REQ3 TX REQ5 TX REQ7 RTREN1 RTREN3 RTREN5 RTREN7 TX1PRI<1:0> TX3PRI<1:0> TX5PRI<1:0> TX7PRI<1:0> TXEN0 TXEN2 TXEN4 TXEN6 TX ABAT0 TX ABAT2 TX ABAT4 TX ABAT6 TX LARB0 TX LARB2 TX LARB4 TX LARB6 TX ERR0 TX ERR2 TX ERR4 TX ERR6 TX REQ0 TX REQ2 TX REQ4 TX REQ6 RTREN0 RTREN2 RTREN4 RTREN6 TX0PRI<1:0> TX2PRI<1:0> TX4PRI<1:0> TX6PRI<1:0> C2TR01CON 0530 C2TR23CON 0532 C2TR45CON 0534 C2TR67CON 0536 C2RXD C2TXD Legend: 0540 0542 dsPIC33F 0000 xxxx xxxx xxxx Recieved Data Word Transmit Data Word x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 3-23: File Name Addr 0500 051E C2BUFPNT1 C2BUFPNT2 C2BUFPNT3 C2BUFPNT4 C2RXM0SID C2RXM0EID C2RXM1SID C2RXM1EID C2RXM2SID C2RXM2EID C2RXF0SID 0520 0522 0524 0526 0530 0532 0534 0536 0538 053A 0540 0542 0544 0546 0548 054A 054C 054E 0550 0552 0554 0556 0558 055A 055C 055E 0560 0562 0564 0566 0568 056A ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Reset s DS70165E-page 62 dsPIC33F See definition when WIN = x F3BP<3:0> F7BP<3:0> F11BP<3:0> F15BP<3:0> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3 EID<15:8> SID<10:3 EID<15:8> SID<10:3 EID<15:8> SID<10:3 EID<15:8> F2BP<3:0> F6BP<3:0> F10BP<3:0> F14BP<3:0> F1BP<3:0> F5BP<3:0> F9BP<3:0> F13BP<3:0> SID<2:0> -- MIDE F0BP<3:0> F4BP<3:0> F8BP<3:0> F12BP<3:0> -- EID<17:16> 0000 0000 0000 0000 xxxx xxxx EID<7:0> SID<2:0> -- MIDE -- EID<17:16> xxxx xxxx EID<7:0> SID<2:0> -- MIDE -- EID<17:16> xxxx xxxx EID<7:0> SID<2:0> -- EXIDE -- EID<17:16> xxxx xxxx Preliminary (c) 2007 Microchip Technology Inc. C2RXF0EID C2RXF1SID C2RXF1EID C2RXF2SID C2RXF2EID C2RXF3SID C2RXF3EID C2RXF4SID C2RXF4EID C2RXF5SID C2RXF5EID C2RXF6SID C2RXF6EID C2RXF7SID C2RXF7EID C2RXF8SID C2RXF8EID C2RXF9SID C2RXF9EID C2RXF10SID C2RXF10EID Legend: EID<7:0> SID<2:0> -- EXIDE -- EID<17:16> xxxx xxxx EID<7:0> SID<2:0> -- EXIDE -- EID<17:16> xxxx xxxx EID<7:0> SID<2:0> -- EXIDE -- EID<17:16> xxxx xxxx EID<7:0> SID<2:0> -- EXIDE -- EID<17:16> xxxx xxxx EID<7:0> SID<2:0> -- EXIDE -- EID<17:16> xxxx xxxx EID<7:0> SID<2:0> -- EXIDE -- EID<17:16> xxxx xxxx EID<7:0> SID<2:0> -- EXIDE -- EID<17:16> xxxx xxxx EID<7:0> SID<2:0> -- EXIDE -- EID<17:16> xxxx xxxx EID<7:0> SID<2:0> -- EXIDE -- EID<17:16> xxxx xxxx EID<7:0> SID<2:0> -- EXIDE -- EID<17:16> xxxx xxxx EID<7:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. (c) 2007 Microchip Technology Inc. TABLE 3-23: File Name C2RXF11SID C2RXF11EID C2RXF12SID C2RXF12EID C2RXF13SID C2RXF13EID C2RXF14SID C2RXF14EID C2RXF15SID C2RXF15EID Legend: Addr 056C 056E 0570 0572 0574 0576 0578 057A 057C 057E ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 (CONTINUED) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 SID<2:0> Bit 5 Bit 4 -- Bit 3 EXIDE Bit 2 -- Bit 1 Bit 0 All Reset s xxxx xxxx -- EID<17:16> xxxx xxxx -- EID<17:16> xxxx xxxx -- EID<17:16> xxxx xxxx -- EID<17:16> xxxx xxxx SID<10:3 EID<15:8> SID<10:3 EID<15:8> SID<10:3 EID<15:8> SID<10:3 EID<15:8> SID<10:3 EID<15:8> EID<17:16> EID<7:0> SID<2:0> -- EXIDE EID<7:0> SID<2:0> -- EXIDE EID<7:0> SID<2:0> -- EXIDE EID<7:0> SID<2:0> -- EXIDE EID<7:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Preliminary dsPIC33F DS70165E-page 63 DS70165E-page 64 dsPIC33F TABLE 3-24: SFR Name DCICON1 DCICON2 DCICON3 DCISTAT TSCON RSCON RXBUF0 RXBUF1 RXBUF2 RXBUF3 TXBUF0 TXBUF1 TXBUF2 Addr. 0280 0282 0284 0286 0288 028C 0290 0292 0294 0296 0298 029A 029C 029E DCI REGISTER MAP Bit 15 DCIEN -- -- -- TSE15 RSE15 Bit 14 -- -- -- -- TSE14 RSE14 Bit 13 DCISIDL -- -- -- TSE13 RSE13 Bit 12 -- -- -- -- TSE12 RSE12 SLOT3 TSE11 RSE11 SLOT2 TSE10 RSE10 SLOT1 TSE9 RSE9 SLOT0 TSE8 RSE8 -- TSE7 RSE7 Bit 11 DLOOP BLEN1 Bit 10 CSCKD BLEN0 Bit 9 CSCKE -- Bit 8 COFSD Bit 7 UNFM Bit 6 CSDOM Bit 5 DJST Bit 4 -- -- Bit 3 -- Bit 2 -- Bit 1 COFSM1 WS<3:0> Bit 0 COFSM0 Reset State 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -- TSE4 RSE4 ROV TSE3 RSE 3 RFUL TSE2 RSE2 TUNF TSE1 RSE1 TMPTY TSE0 RSE0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 COFSG<3:0> BCG<11:0> -- TSE6 RSE6 -- TSE5 RSE5 Receive Buffer #0 Data Register Receive Buffer #1 Data Register Receive Buffer #2 Data Register Receive Buffer #3 Data Register Transmit Buffer #0 Data Register Transmit Buffer #1 Data Register Transmit Buffer #2 Data Register Transmit Buffer #3 Data Register Preliminary (c) 2007 Microchip Technology Inc. TXBUF3 Legend: Note 1: -- = unimplemented, read as `0'. Refer to the "dsPIC30F Family Reference Manual" (DS70046) for descriptions of register bit fields. TABLE 3-25: File Name TRISA PORTA LATA ODCA(2) Legend: Note 1: Addr 02C0 02C2 02C4 06C0 PORTA REGISTER MAP(1) Bit 15 TRISA15 RA15 LATA15 ODCA15 Bit 14 TRISA14 RA14 LATA14 ODCA14 Bit 13 TRISA13 RA13 LATA13 ODCA13 Bit 12 TRISA12 RA12 LATA12 ODCA12 Bit 11 -- -- -- -- Bit 10 TRISA10 RA10 LATA10 -- Bit 9 TRISA9 RA9 LATA9 -- Bit 8 -- -- -- -- Bit 7 TRISA7 RA7 LATA7 -- Bit 6 TRISA6 RA6 LATA6 -- Bit 5 TRISA5 RA5 LATA5 ODCA5 Bit 4 TRISA4 RA4 LATA4 ODCA4 Bit 3 TRISA3 RA3 LATA3 ODCA3 Bit 2 TRISA2 RA2 LATA2 ODCA2 Bit 1 TRISA1 RA1 LATA1 ODCA1 Bit 0 TRISA0 RA0 LATA0 ODCA0 All Resets D6C0 xxxx xxxx xxxx x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. TABLE 3-26: File Name TRISB PORTB LATB Legend: Note 1: Addr 02C6 02C8 02CA PORTB REGISTER MAP(1) Bit 15 TRISB15 RB15 LATB15 Bit 14 TRISB14 RB14 LATB14 Bit 13 TRISB13 RB13 LATB13 Bit 12 TRISB12 RB12 LATB12 Bit 11 TRISB11 RB11 LATB11 Bit 10 TRISB10 RB10 LATB10 Bit 9 TRISB9 RB9 LATB9 Bit 8 TRISB8 RB8 LATB8 Bit 7 TRISB7 RB7 LATB7 Bit 6 TRISB6 RB6 LATB6 Bit 5 TRISB5 RB5 LATB5 Bit 4 TRISB4 RB4 LATB4 Bit 3 TRISB3 RB3 LATB3 Bit 2 TRISB2 RB2 LATB2 Bit 1 TRISB1 RB1 LATB1 Bit 0 TRISB0 RB0 LATB0 All Resets FFFF xxxx xxxx x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. (c) 2007 Microchip Technology Inc. TABLE 3-27: File Name TRISC PORTC LATC Legend: Note 1: Addr 02CC 02CE 02D0 PORTC REGISTER MAP(1) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 -- -- -- Bit 10 -- -- -- Bit 9 -- -- -- Bit 8 -- -- -- Bit 7 -- -- -- Bit 6 -- -- -- Bit 5 -- -- -- Bit 4 TRISC4 RC4 LATC4 Bit 3 TRISC3 RC3 LATC3 Bit 2 TRISC2 RC2 LATC2 Bit 1 TRISC1 RC1 LATC1 Bit 0 -- -- -- All Resets F01E xxxx xxxx TRISC15 TRISC14 TRISC13 TRISC12 RC15 LATC15 RC14 LATC14 RC13 LATC13 RC12 LATC12 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. TABLE 3-28: File Name TRISD PORTD LATD ODCD Legend: Note 1: Addr 02D2 02D4 02D6 06D2 PORTD REGISTER MAP(1) Bit 15 TRISD15 RD15 LATD15 ODCD15 Bit 14 TRISD14 RD14 LATD14 ODCD14 Bit 13 TRISD13 RD13 LATD13 ODCD13 Bit 12 TRISD12 RD12 LATD12 ODCD12 Bit 11 TRISD11 RD11 LATD11 ODCD11 Bit 10 TRISD10 RD10 LATD10 ODCD10 Bit 9 TRISD9 RD9 LATD9 ODCD9 Bit 8 TRISD8 RD8 LATD8 ODCD8 Bit 7 TRISD7 RD7 LATD7 ODCD7 Bit 6 TRISD6 RD6 LATD6 ODCD6 Bit 5 TRISD5 RD5 LATD5 ODCD5 Bit 4 TRISD4 RD4 LATD4 ODCD4 Bit 3 TRISD3 RD3 LATD3 ODCD3 Bit 2 TRISD2 RD2 LATD2 ODCD2 Bit 1 TRISD1 RD1 LATD1 ODCD1 Bit 0 TRISD0 RD0 LATD0 ODCD0 All Resets FFFF xxxx xxxx xxxx x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. Preliminary DS70165E-page 65 TABLE 3-29: File Name TRISE PORTE LATE Legend: Note 1: Addr 02D8 02DA 02DC PORTE REGISTER MAP(1) Bit 15 -- -- -- Bit 14 -- -- -- Bit 13 -- -- -- Bit 12 -- -- -- Bit 11 -- -- -- Bit 10 -- -- -- Bit 9 -- -- -- Bit 8 -- -- -- Bit 7 TRISE7 RE7 LATE7 Bit 6 TRISE6 RE6 LATE6 Bit 5 TRISE5 RE5 LATE5 Bit 4 TRISE4 RE4 LATE4 Bit 3 TRISE3 RE3 LATE3 Bit 2 TRISE2 RE2 LATE2 Bit 1 TRISE1 RE1 LATE1 Bit 0 TRISE0 RE0 LATE0 All Resets 03FF xxxx xxxx x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. TABLE 3-30: File Name TRISF PORTF LATF ODCF Legend: Note 1: Addr 02DE 02E0 02E2 06DE PORTF REGISTER MAP(1) Bit 15 -- -- -- -- Bit 14 -- -- -- -- Bit 13 TRISF13 RF13 LATF13 ODCF13 Bit 12 TRISF12 RF12 LATF12 ODCF12 Bit 11 -- -- -- -- Bit 10 -- -- -- -- Bit 9 -- -- -- -- Bit 8 TRISF8 RF8 LATF8 ODCF8 Bit 7 TRISF7 RF7 LATF7 ODCF7 Bit 6 TRISF6 RF6 LATF6 ODCF6 Bit 5 TRISF5 RF5 LATF5 ODCF5 Bit 4 TRISF4 RF4 LATF4 ODCF4 Bit 3 TRISF3 RF3 LATF3 ODCF3 Bit 2 TRISF2 RF2 LATF2 ODCF2 Bit 1 TRISF1 RF1 LATF1 ODCF1 Bit 0 TRISF0 RF0 LATF0 ODCF0 All Resets 31FF xxxx xxxx xxxx dsPIC33F x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. TABLE 3-31: File Name TRISG PORTG LATG ODCG Legend: Note 1: Addr 02E4 02E6 02E8 06E4 PORTG REGISTER MAP(1) Bit 15 TRISG15 RG15 LATG15 ODCG15 Bit 14 TRISG14 RG14 LATG14 ODCG14 Bit 13 TRISG13 RG13 LATG13 ODCG13 Bit 12 TRISG12 RG12 LATG12 ODCG12 Bit 11 -- -- -- -- Bit 10 -- -- -- -- Bit 9 TRISG9 RG9 LATG9 ODCG9 Bit 8 TRISG8 RG8 LATG8 ODCG8 Bit 7 TRISG7 RG7 LATG7 ODCG7 Bit 6 TRISG6 RG6 LATG6 ODCG6 Bit 5 -- -- -- -- Bit 4 -- -- -- -- Bit 3 TRISG3 RG3 LATG3 ODCG3 Bit 2 TRISG2 RG2 LATG2 ODCG2 Bit 1 TRISG1 RG1 LATG1 ODCG1 Bit 0 TRISG0 RG0 LATG0 ODCG0 All Resets F3CF xxxx xxxx xxxx DS70165E-page 66 dsPIC33F x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. TABLE 3-32: File Name RCON OSCCON CLKDIV PLLFBD Addr 0740 0742 0744 0746 0748 SYSTEM CONTROL REGISTER MAP Bit 15 TRAPR -- ROI -- -- -- -- Bit 14 IOPUWR Bit 13 -- COSC<2:0> DOZE<2:0> -- -- -- -- Bit 12 -- Bit 11 -- -- DOZEN -- -- -- -- Bit 10 -- Bit 9 -- NOSC<2:0> FRCDIV<2:0> -- -- -- -- -- Bit 8 VREGS Bit 7 EXTR CLKLOCK Bit 6 SWR -- Bit 5 SWDTEN LOCK -- PLLDIV<8:0> TUN<5:0> Bit 4 WDTO -- Bit 3 SLEEP CF Bit 2 IDLE -- Bit 1 BOR LPOSCEN Bit 0 POR OSWEN All Resets xxxx(1) 0300(2) 0040 0030 0000 PLLPOST<1:0> PLLPRE<4::0> Preliminary (c) 2007 Microchip Technology Inc. OSCTUN Legend: Note 1: 2: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. RCON register Reset values dependent on type of Reset. OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset. TABLE 3-33: File Name NVMCON NVMKEY Legend: Note 1: Addr 0760 0766 NVM REGISTER MAP Bit 15 WR -- Bit 14 WREN -- Bit 13 WRERR -- Bit 12 -- -- Bit 11 -- -- Bit 10 -- -- Bit 9 -- -- Bit 8 -- -- Bit 7 -- Bit 6 ERASE Bit 5 -- Bit 4 -- NVMKEY<7:0> Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000(1) 0000 NVMOP<3:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. TABLE 3-34: File Name PMD1 PMD2 PMD3 Legend: Addr 0770 0772 0774 PMD REGISTER MAP Bit 15 T5MD IC8MD T9MD Bit 14 T4MD IC7MD T8MD Bit 13 T3MD IC6MD T7MD Bit 12 T2MD IC5MD T6MD Bit 11 T1MD IC4MD -- Bit 10 QEIMD IC3MD -- Bit 9 PWMMD IC2MD -- Bit 8 DCIMD IC1MD -- Bit 7 I2C1MD OC8MD -- Bit 6 U2MD OC7MD -- Bit 5 U1MD OC6MD -- Bit 4 SPI2MD OC5MD -- Bit 3 SPI1MD OC4MD -- Bit 2 C2MD OC3MD -- Bit 1 C1MD OC2MD I2C2MD Bit 0 AD1MD OC1MD AD2MD All Resets 0000 0000 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. dsPIC33F 3.2.7 SOFTWARE STACK 3.2.8 DATA RAM PROTECTION FEATURE In addition to its use as a working register, the W15 register in the dsPIC33F devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 3-6. For a PC push during any CALL instruction, the MSb of the PC is zero-extended before the push, ensuring that the MSb is always clear. Note: A PC push during exception processing concatenates the SRL register to the MSb of the PC prior to the push. The dsPIC33F product family supports Data RAM protection features which enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security. BSRAM (Secure RAM segment for BS) is accessible only from the Boot Segment Flash code when enabled. SSRAM (Secure RAM segment for RAM) is accessible only from the Secure Segment Flash code when enabled. See Table 3-1 for an overview of the BSRAM and SSRAM SFRs. 3.3 Instruction Addressing Modes The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> is forced to `0' because all stack operations must be word-aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a stack error trap when the stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the value 0x1FFE. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0x0800. This prevents the stack from interfering with the Special Function Register (SFR) space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. The addressing modes in Table 3-35 form the basis of the addressing modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions are somewhat different from those in the other instruction types. 3.3.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (Near Data Space). Most file register instructions employ a working register, W0, which is denoted as WREG in these instructions. The destination is typically either the same file register or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can access the entire data space. 3.3.2 MCU INSTRUCTIONS The 3-operand MCU instructions are of the form: Operand 3 = Operand 1 FIGURE 3-6: 0x0000 15 CALL STACK FRAME 0 Stack Grows Towards Higher Address PC<15:0> 000000000 PC<22:16> W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH : [W15++] (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 67 dsPIC33F TABLE 3-35: FUNDAMENTAL ADDRESSING MODES SUPPORTED Description The address of the file register is specified explicitly. The contents of a register are accessed directly. The contents of Wn forms the EA. The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. The sum of Wn and a literal forms the EA. and W10 and W11 will always be directed to the Y AGU. The effective addresses generated (before and after modification) must, therefore, be valid addresses within X data space for W8 and W9 and Y data space for W10 and W11. Note: Register Indirect with Register Offset Addressing mode is only available for W9 (in X space) and W11 (in Y space). Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset 3.3.3 MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the Addressing modes supported by most MCU instructions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode. Note: For the MOV instructions, the Addressing mode specified in the instruction can differ for the source and destination EA. However, the 4-bit Wb (Register Offset) field is shared between both source and destination (but typically only used by one). In summary, the following addressing modes are supported by the MAC class of instructions: * * * * * Register Indirect Register Indirect Post-Modified by 2 Register Indirect Post-Modified by 4 Register Indirect Post-Modified by 6 Register Indirect with Register Offset (Indexed) In summary, the following Addressing modes are supported by move and accumulator instructions: * * * * * * * * Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset (Indexed) Register Indirect with Literal Offset 8-bit Literal 16-bit Literal Note: Not all instructions support all the Addressing modes given above. Individual instructions may support different subsets of these Addressing modes. 3.3.5 OTHER INSTRUCTIONS Besides the various addressing modes outlined above, some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. 3.4 Modulo Addressing 3.3.4 MAC INSTRUCTIONS The dual source operand DSP instructions (CLR, ED, EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred to as MAC instructions, utilize a simplified set of addressing modes to allow the user to effectively manipulate the data pointers through register indirect tables. The 2-source operand prefetch registers must be members of the set {W8, W9, W10, W11}. For data reads, W8 and W9 are always directed to the X RAGU Modulo Addressing mode is a method of providing an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms. Modulo Addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into program space) and Y data spaces. Modulo Addressing can operate on any W register pointer. However, it is not DS70165E-page 68 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F advisable to use W14 or W15 for Modulo Addressing since these two registers are used as the Stack Frame Pointer and Stack Pointer, respectively. In general, any particular circular buffer can only be configured to operate in one direction as there are certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing buffers), based upon the direction of the buffer. The only exception to the usage restrictions is for buffers which have a power-of-2 length. As these buffers satisfy the start and end address criteria, they may operate in a bidirectional mode (i.e., address boundary checks will be performed on both the lower and upper address boundaries). The length of a circular buffer is not directly specified. It is determined by the difference between the corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes). 3.4.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control register, MODCON<15:0>, contains enable flags as well as a W register field to specify the W Address registers. The XWM and YWM fields select which registers will operate with Modulo Addressing. If XWM = 15, X RAGU and X WAGU Modulo Addressing is disabled. Similarly, if YWM = 15, Y AGU Modulo Addressing is disabled. The X Address Space Pointer W register (XWM), to which Modulo Addressing is to be applied, is stored in MODCON<3:0> (see Table 3-1). Modulo Addressing is enabled for X data space when XWM is set to any value other than `15' and the XMODEN bit is set at MODCON<15>. The Y Address Space Pointer W register (YWM) to which Modulo Addressing is to be applied is stored in MODCON<7:4>. Modulo Addressing is enabled for Y data space when YWM is set to any value other than 3.4.1 START AND END ADDRESS The Modulo Addressing scheme requires that a starting and ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table 3-1). Note: Y space Modulo Addressing EA calculations assume word sized data (LSb of every EA is always clear). FIGURE 3-7: Byte Address MODULO ADDRESSING OPERATION EXAMPLE MOV MOV MOV MOV MOV MOV MOV MOV #0x1100, W0 W0, XMODSRT #0x1163, W0 W0, MODEND #0x8001, W0 W0, MODCON #0x0000, W0 #0x1110, W1 ;set modulo start address ;set modulo end address ;enable W1, X AGU for modulo ;W0 holds buffer fill value ;point W1 to buffer ;fill the 50 buffer locations ;fill the next location ;increment the fill value 0x1100 DO AGAIN, #0x31 MOV W0, [W1++] AGAIN: INC W0, W0 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 69 dsPIC33F 3.4.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. It is important to realize that the address boundaries check for addresses less than, or greater than, the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes may, therefore, jump beyond boundaries and still be adjusted correctly. Note: The modulo corrected effective address is written back to the register only when Pre-Modify or Post-Modify Addressing mode is used to compute the effective address. When an address offset (e.g., [W7+W2]) is used, Modulo Address correction is performed but the contents of the register remain unchanged. If the length of a bit-reversed buffer is M = 2N bytes, the last `N' bits of the data buffer start address must be zeros. XB<14:0> is the Bit-Reversed Address modifier, or `pivot point', which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT data buffer size. Note: All bit-reversed EA calculations assume word sized data (LSb of every EA is always clear). The XB value is scaled accordingly to generate compatible (byte) addresses. 3.5 Bit-Reversed Addressing Bit-Reversed Addressing mode is intended to simplify data re-ordering for radix-2 FFT algorithms. It is supported by the X AGU for data writes only. The modifier, which may be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier. When enabled, Bit-Reversed Addressing is only executed for Register Indirect with Pre-Increment or Post-Increment Addressing and word sized data writes. It will not function for any other addressing mode or for byte sized data and normal addresses are generated instead. When Bit-Reversed Addressing is active, the W Address Pointer is always added to the address modifier (XB) and the offset associated with the Register Indirect Addressing mode is ignored. In addition, as word sized data is a requirement, the LSb of the EA is ignored (and always clear). Note: Modulo Addressing and Bit-Reversed Addressing should not be enabled together. In the event that the user attempts to do so, Bit-Reversed Addressing will assume priority when active for the X WAGU and X WAGU Modulo Addressing will be disabled. However, Modulo Addressing will continue to function in the X RAGU. 3.5.1 BIT-REVERSED ADDRESSING IMPLEMENTATION Bit-Reversed Addressing mode is enabled when: 1. BWM bits (W register selection) in the MODCON register are any value other than `15' (the stack cannot be accessed using Bit-Reversed Addressing). The BREN bit is set in the XBREV register. The addressing mode used is Register Indirect with Pre-Increment or Post-Increment. 2. 3. If Bit-Reversed Addressing has already been enabled by setting the BREN (XBREV<15>) bit, then a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. DS70165E-page 70 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F FIGURE 3-8: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 3-36: A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit-Reversed Address A1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Decimal 0 8 4 12 2 10 6 14 1 9 5 13 3 11 7 15 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 71 dsPIC33F 3.6 Interfacing Program and Data Memory Spaces 3.6.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG<7> = 0) or the configuration memory (TBLPAG<7> = 1). For remapping operations, the 8-bit Program Space Visibility register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is `1', PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area. Table 3-37 and Figure 3-9 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word. The dsPIC33F architecture uses a 24-bit wide program space and a 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the dsPIC33F architecture provides two methods by which program space can be accessed during operation: * Using table instructions to access individual bytes or words anywhere in the program space * Remapping a portion of the program space into the data space (Program Space Visibility) Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated from time to time. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. It can only access the least significant word of the program word. TABLE 3-37: PROGRAM SPACE ADDRESS CONSTRUCTION Access Space User User Configuration Program Space Address <23> 0 0xx xxxx TBLPAG<7:0> 0xxx xxxx TBLPAG<7:0> 1xxx xxxx 0 0 PSVPAG<7:0> xxxx xxxx <22:16> <15> PC<22:1> xxxx xxxx xxxx xxx0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<14:0>(1) xxx xxxx xxxx xxxx <14:1> <0> 0 Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write) Program Space Visibility (Block Remap/Read) Note 1: User Data EA<15> is always `1' in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. DS70165E-page 72 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F FIGURE 3-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) 0 Program Counter 23 bits 0 EA Table Operations(2) 1/0 TBLPAG 8 bits 24 bits 16 bits 1/0 Select Program Space (Remapping) Visibility(1) 0 PSVPAG 8 bits 1 EA 0 15 bits 23 bits User/Configuration Space Select Byte Select Note 1: The LSb of program space addresses is always fixed as `0' in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 73 dsPIC33F 3.6.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16>) to a data address. Note that D<15:8>, the `phantom byte', will always be `0'. In Byte mode, it maps the upper or lower byte of the program word to D<7:0> of the data address, as above. Note that the data will always be `0' when the upper `phantom' byte is selected (Byte Select = 1). In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 4.0 "Flash Program Memory". For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG<7> = 0, the table page is located in the user memory space. When TBLPAG<7> = 1, the page is located in configuration space. The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit word wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space which contains the least significant data word and TBLRDH and TBLWTH access the space which contains the upper data byte. Two table instructions are provided to move byte or word sized (16-bit) data to and from program space. Both function as either byte or word operations. 1. TBLRDL (Table Read Low): In Word mode, it maps the lower word of the program space location (P<15:0>) to a data address (D<15:0>). In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is `1'; the lower byte is selected when it is `0'. FIGURE 3-10: TBLPAG ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space 02 23 15 0 0x000000 00000000 00000000 23 16 8 0 0x020000 0x030000 00000000 00000000 `Phantom' Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area. 0x800000 DS70165E-page 74 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 3.6.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with `1111 1111' or `0000 0000' to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes. The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H). Program space access through the data space occurs if the Most Significant bit of the data space EA is `1' and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON<2>). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. Note that by incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads to this area add an additional cycle to the instruction being executed, since two program memory fetches are required. Although each data space address, 8000h and higher, maps directly into a corresponding program memory address (see Figure 3-11), only the lower 16 bits of the For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions require one instruction cycle in addition to the specified execution time. All other instructions require two instruction cycles in addition to the specified execution time. For operations that use PSV, which are executed inside a REPEAT loop, there will be some instances that require two instruction cycles in addition to the specified execution time of the instruction: * Execution in the first iteration * Execution in the last iteration * Execution prior to exiting the loop due to an interrupt * Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle. FIGURE 3-11: PROGRAM SPACE VISIBILITY OPERATION When CORCON<2> = 1 and EA<15> = 1: Program Space PSVPAG 02 23 15 0 0x000000 0x010000 0x018000 The data in the page designated by PSVPAG is mapped into the upper half of the data memory space... Data Space 0x0000 Data EA<14:0> 0x8000 PSV Area ...while the lower 15 bits of the EA specify an exact address within 0xFFFF the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. 0x800000 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 75 dsPIC33F NOTES: DS70165E-page 76 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 4.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user can write program memory data either in blocks or `rows' of 64 instructions (192 bytes) at a time or a single program memory word, and erase program memory in blocks or `pages' of 512 instructions (1536 bytes) at a time. The dsPIC33F devices contain internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire VDD range. Flash memory can be programmed in two ways: 1. 2. In-Circuit Serial ProgrammingTM (ICSPTM) programming capability Run-Time Self-Programming (RTSP) 4.1 Table Instructions and Flash Programming ICSP allows a dsPIC33F device to be serially programmed while in the end application circuit. This is simply done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGC1/PGD1, PGC2/PGD2 or PGC3/PGD3), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using bits<7:0> of the TBLPAG register and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 4-1. The TBLRDL and the TBLWTL instructions are used to read or write to bits<15:0> of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits<23:16> of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode. FIGURE 4-1: ADDRESSING FOR TABLE REGISTERS 24 bits Using Program Counter 0 Program Counter 0 Working Reg EA Using Table Instruction 1/0 TBLPAG Reg 8 bits 16 bits User/Configuration Space Select 24-bit EA Byte Select (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 77 dsPIC33F 4.2 RTSP Operation 4.3 Control Registers The dsPIC33F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. Table 26-11, DC Characteristics: Program Memory shows typical erase and programming times. The 8row erase pages and single row write rows are edgealigned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. The program memory implements holding buffers that can contain 64 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the buffers in sequential order. The instruction words loaded must always be from a group of 64 boundary. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions are required to load the instructions. All of the table write operations are single-word writes (two instruction cycles) because only the buffers are written. A programming cycle is required for programming each row. There are two SFRs used to read and write the program Flash memory: NVMCON and NVMKEY. The NVMCON register (Register 4-1) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle. NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user must consecutively write 55h and AAh to the NVMKEY register. Refer to Section 4.4 "Programming Operations" for further details. 4.4 Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. A programming operation is nominally 4 ms in duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. DS70165E-page 78 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 4-1: R/SO-0(1) WR bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 SO = Satiable only bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0(1) ERASE U-0 -- U-0 -- R/W-0(1) R/W-0(1) R/W-0(1) NVMCON: FLASH MEMORY CONTROL REGISTER R/W-0(1) WREN R/W-0(1) WRERR U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0(1) bit 0 NVMOP<3:0>(2) WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. 0 = Program or erase operation is complete and inactive WREN: Write Enable bit 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally Unimplemented: Read as `0' ERASE: Erase/Program Enable bit 1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command 0 = Perform the program operation specified by NVMOP<3:0> on the next WR command Unimplemented: Read as `0' NVMOP<3:0>: NVM Operation Select bits(2) 1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0) 1110 = Reserved 1101 = Erase General Segment and FGS Configuration register (ERASE = 1) or no operation (ERASE = 0) 1100 = Erase Secure Segment and FSS Configuration register (ERASE = 1) or no operation (ERASE = 0) 1011 = Reserved 0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1) 0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0) 0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1) 0000 = Program or erase a single Configuration register byte These bits can only be reset on POR. All other combinations of NVMOP<3:0> are unimplemented. bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3-0 Note 1: 2: (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 79 dsPIC33F 4.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. The user can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the block (see Example 4-1): a) Set the NVMOP bits (NVMCON<3:0>) to `0010' to configure for block erase. Set the ERASE (NVMCON<6>) and WREN (NVMCON<14>) bits. b) Write the starting address of the page to be erased into the TBLPAG and W registers. c) Write 55h to NVMKEY. d) Write AAh to NVMKEY. e) Set the WR bit (NVMCON<15>). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-2). Write the program block to Flash memory: a) Set the NVMOP bits to `0001' to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 55h to NVMKEY. c) Write AAh to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory. 6. For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 4-3. EXAMPLE 4-1: ERASING A PROGRAM MEMORY PAGE ; ; Initialize NVMCON ; ; ; ; ; ; ; ; ; ; ; ; ; Set up NVMCON for block erase operation MOV #0x4042, W0 MOV W0, NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 MOV W0, TBLPAG MOV #tbloffset(PROG_ADDR), W0 TBLWTL W0, [W0] DISI #5 MOV MOV MOV MOV BSET NOP NOP #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR Initialize PM Page Boundary SFR Initialize in-page EA[15:0] pointer Set base address of erase block Block all interrupts with priority <7 for next 5 instructions Write the 55 key Write the AA key Start the erase sequence Insert two NOPs after the erase command is asserted DS70165E-page 80 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F EXAMPLE 4-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; ; Write PM low word into program latch TBLWTL W2, [W0] ; Write PM high byte into program latch TBLWTH W3, [W0++] * * * ; 63rd_program_word MOV #LOW_WORD_31, W2 ; MOV #HIGH_BYTE_31, W3 ; ; Write PM low word into program latch TBLWTL W2, [W0] ; Write PM high byte into program latch TBLWTH W3, [W0++] EXAMPLE 4-3: DISI MOV MOV MOV MOV BSET NOP NOP #5 INITIATING A PROGRAMMING SEQUENCE ; Block all interrupts with priority <7 ; for next 5 instructions ; ; ; ; ; ; Write the 55 key Write the AA key Start the erase sequence Insert two NOPs after the erase command is asserted #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 81 dsPIC33F NOTES: DS70165E-page 82 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 5.0 Note: RESETS This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). Note: Refer to the specific peripheral or CPU section of this manual for register Reset states. The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources: * * * * * * * POR: Power-on Reset BOR: Brown-out Reset MCLR: Master Clear Pin Reset SWR: RESET Instruction WDT: Watchdog Timer Reset TRAPR: Trap Conflict Reset IOPUWR: Illegal Opcode and Uninitialized W Register Reset All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 5-1). A POR will clear all bits, except for the POR bit (RCON<0>), that are set. The user can set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software does not cause a device Reset to occur. The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. The function of these bits is discussed in other sections of this manual. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful. A simplified block diagram of the Reset module is shown in Figure 5-1. Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets. FIGURE 5-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle VDD Rise Detect VDD Internal Regulator BOR POR SYSRST Trap Conflict Illegal Opcode Uninitialized W Register (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 83 dsPIC33F REGISTER 5-1: R/W-0 TRAPR bit 15 R/W-0 EXTR bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 SWR R/W-0 SWDTEN (2) RCON: RESET CONTROL REGISTER(1) R/W-0 IOPUWR U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 VREGS bit 8 R/W-0 WDTO R/W-0 SLEEP R/W-0 IDLE R/W-1 BOR R/W-1 POR bit 0 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred Unimplemented: Read as `0' VREGS: Voltage Regulator Standby During Sleep bit 1 = Voltage regulator goes into Standby mode during Sleep 0 = Voltage regulator is active during Sleep EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode IDLE: Wake-up from Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is `1' (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. bit 14 bit 13-9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 Note 1: 2: DS70165E-page 84 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 5-1: bit 0 RCON: RESET CONTROL REGISTER(1) POR: Power-on Reset Flag bit 1 = A Power-up Reset has occurred 0 = A Power-up Reset has not occurred All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is `1' (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. Note 1: 2: TABLE 5-1: RESET FLAG BIT OPERATION Flag Bit Setting Event Trap conflict event Illegal opcode or uninitialized W register access MCLR Reset RESET instruction WDT time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction BOR POR POR POR POR POR PWRSAV instruction, POR POR POR -- -- Clearing Event TRAPR (RCON<15>) IOPUWR (RCON<14>) EXTR (RCON<7>) SWR (RCON<6>) WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) BOR (RCON<1> POR (RCON<0>) Note: All Reset flag bits may be set or cleared by the user software. 5.1 Clock Source Selection at Reset 5.2 Device Reset Times If clock switching is enabled, the system clock source at device Reset is chosen, as shown in Table 5-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to Section 8.0 "Oscillator Configuration" for further details. The Reset times for various types of device Reset are summarized in Table 5-3. The system Reset signal, SYSRST, is released after the POR and PWRT delay times expire. The time at which the device actually begins to execute code also depends on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and the PLL lock time. The OST and PLL lock times occur in parallel with the applicable SYSRST delay times. The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released. TABLE 5-2: OSCILLATOR SELECTION vs. TYPE OF RESET (CLOCK SWITCHING ENABLED) Clock Source Determinant Oscillator Configuration bits (FNOSC<2:0>) COSC Control bits (OSCCON<14:12>) Reset Type POR BOR MCLR WDTR SWR (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 85 dsPIC33F TABLE 5-3: Reset Type POR RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Clock Source EC, FRC, LPRC ECPLL, FRCPLL XT, HS, SOSC XTPLL, HSPLL SYSRST Delay TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TRST TRST TRST TRST TRST TRST System Clock Delay -- TLOCK TOST TOST + TLOCK -- -- -- -- -- -- FSCM Delay -- TFSCM TFSCM TFSCM -- -- -- -- -- -- Notes 1, 2, 3 1, 2, 3, 5, 6 1, 2, 3, 4, 6 1, 2, 3, 4, 5, 6 3 3 3 3 3 3 MCLR WDT Software Illegal Opcode Uninitialized W Trap Conflict Note 1: 2: Any Clock Any Clock Any Clock Any Clock Any Clock Any Clock 3: 4: 5: 6: TPOR = Power-on Reset delay (10 s nominal). TSTARTUP = Conditional POR delay of 20 s nominal (if on-chip regulator is enabled) or 64 ms nominal Power-up Timer delay (if regulator is disabled). TSTARTUP is also applied to all returns from powered-down states, including waking from Sleep mode, only if the regulator is enabled. TRST = Internal state Reset time (20 s nominal). TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the oscillator clock to the system. TLOCK = PLL lock time (20 s nominal). TFSCM = Fail-Safe Clock Monitor delay (100 s nominal). 5.2.1 POR AND LONG OSCILLATOR START-UP TIMES 5.2.2.1 FSCM Delay for Crystal and PLL Clock Sources The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: * The oscillator circuit has not begun to oscillate. * The Oscillator Start-up Timer has not expired (if a crystal oscillator is used). * The PLL has not achieved a lock (if PLL is used). The device will not begin to execute code until a valid clock source has been released to the system. Therefore, the oscillator and PLL start-up delays must be considered when the Reset delay time must be known. When the system clock source is provided by a crystal oscillator and/or the PLL, a small delay, TFSCM, is automatically inserted after the POR and PWRT delay times. The FSCM does not begin to monitor the system clock source until this delay expires. The FSCM delay time is nominally 100 s and provides additional time for the oscillator and/or PLL to stabilize. In most cases, the FSCM delay prevents an oscillator failure trap at a device Reset when the PWRT is disabled. 5.3 Special Function Register Reset States 5.2.2 FAIL-SAFE CLOCK MONITOR (FSCM) AND DEVICE RESETS Most of the Special Function Registers (SFRs) associated with the CPU and peripherals are reset to a particular value at a device Reset. The SFRs are grouped by their peripheral or CPU function and their Reset values are specified in each section of this manual. The Reset value for each SFR does not depend on the type of Reset, with the exception of two registers. The Reset value for the Reset Control register, RCON, depends on the type of device Reset. The Reset value for the Oscillator Control register, OSCCON, depends on the type of Reset and the programmed values of the oscillator Configuration bits in the FOSC Configuration register. If the FSCM is enabled, it begins to monitor the system clock source when SYSRST is released. If a valid clock source is not available at this time, the device automatically switches to the FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine. DS70165E-page 86 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 6.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). 6.1.1 ALTERNATE VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1. Access to the AIVT is provided by the ALTIVT control bit (INTCON2<15>). If the ALTIVT bit is set, all interrupt and exception processes use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT supports debugging by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT. The dsPIC33F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the dsPIC33F CPU. It has the following features: Up to 8 processor exceptions and software traps 7 user-selectable priority levels Interrupt Vector Table (IVT) with up to 118 vectors A unique vector for each interrupt or exception source * Fixed priority within a specified user priority level * Alternate Interrupt Vector Table (AIVT) for debug support * Fixed interrupt entry and return latencies * * * * 6.2 Reset Sequence 6.1 Interrupt Vector Table The Interrupt Vector Table (IVT) is shown in Figure 6-1. The IVT resides in program memory, starting at location 000004h. The IVT contains 126 vectors consisting of 8 nonmaskable trap vectors plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). Interrupt vectors are prioritized in terms of their natural priority; this priority is linked to their position in the vector table. All other things being equal, lower addresses have a higher natural priority. For example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address. dsPIC33F devices implement up to 67 unique interrupts and 5 nonmaskable traps. These are summarized in Table 6-1 and Table 6-2. A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The dsPIC33F device clears its registers in response to a Reset, which forces the PC to zero. The digital signal controller then begins program execution at location 0x000000. The user programs a GOTO instruction at the Reset address which redirects program execution to the appropriate start-up routine. Note: Any unimplemented or unused vector locations in the IVT and AIVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 87 dsPIC33F FIGURE 6-1: dsPIC33F INTERRUPT VECTOR TABLE Reset - GOTO Instruction Reset - GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 Start of Code 0x000000 0x000002 0x000004 0x000014 Decreasing Natural Order Priority 0x00007C 0x00007E 0x000080 Interrupt Vector Table (IVT)(1) 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 Alternate Interrupt Vector Table (AIVT)(1) 0x00017C 0x00017E 0x000180 0x0001FE 0x000200 Note 1: See Table 6-1 for the list of implemented interrupt vectors. DS70165E-page 88 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F TABLE 6-1: Vector Number 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 INTERRUPT VECTORS Interrupt Request (IRQ) Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 IVT Address 0x000014 0x000016 0x000018 0x00001A 0x00001C 0x00001E 0x000020 0x000022 0x000024 0x000026 0x000028 0x00002A 0x00002C 0x00002E 0x000030 0x000032 0x000034 0x000036 0x000038 0x00003A 0x00003C 0x00003E 0x000040 0x000042 0x000044 0x000046 0x000048 0x00004A 0x00004C 0x00004E 0x000050 0x000052 0x000054 0x000056 0x000058 0x00005A 0x00005C 0x00005E 0x000060 0x000062 0x000064 0x000066 0x000068 0x00006A 0x00006C 0x00006E AIVT Address 0x000114 0x000116 0x000118 0x00011A 0x00011C 0x00011E 0x000120 0x000122 0x000124 0x000126 0x000128 0x00012A 0x00012C 0x00012E 0x000130 0x000132 0x000134 0x000136 0x000138 0x00013A 0x00013C 0x00013E 0x000140 0x000142 0x000144 0x000146 0x000148 0x00014A 0x00014C 0x00014E 0x000150 0x000152 0x000154 0x000156 0x000158 0x00015A 0x00015C 0x00015E 0x000160 0x000162 0x000164 0x000166 0x000168 0x00016A 0x00016C 0x00016E Interrupt Source INT0 - External Interrupt 0 IC1 - Input Compare 1 OC1 - Output Compare 1 T1 - Timer1 DMA0 - DMA Channel 0 IC2 - Input Capture 2 OC2 - Output Compare 2 T2 - Timer2 T3 - Timer3 SPI1E - SPI1 Error SPI1 - SPI1 Transfer Done U1RX - UART1 Receiver U1TX - UART1 Transmitter ADC1 - ADC 1 DMA1 - DMA Channel 1 Reserved SI2C1 - I2C1 Slave Events MI2C1 - I2C1 Master Events Reserved Change Notification Interrupt INT1 - External Interrupt 1 ADC2 - ADC 2 IC7 - Input Capture 7 IC8 - Input Capture 8 DMA2 - DMA Channel 2 OC3 - Output Compare 3 OC4 - Output Compare 4 T4 - Timer4 T5 - Timer5 INT2 - External Interrupt 2 U2RX - UART2 Receiver U2TX - UART2 Transmitter SPI2E - SPI2 Error SPI1 - SPI1 Transfer Done C1RX - ECAN1 Receive Data Ready C1 - ECAN1 Event DMA3 - DMA Channel 3 IC3 - Input Capture 3 IC4 - Input Capture 4 IC5 - Input Capture 5 IC6 - Input Capture 6 OC5 - Output Compare 5 OC6 - Output Compare 6 OC7 - Output Compare 7 OC8 - Output Compare 8 Reserved (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 89 dsPIC33F TABLE 6-1: Vector Number 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80-125 INTERRUPT VECTORS (CONTINUED) Interrupt Request (IRQ) Number 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72-117 IVT Address 0x000070 0x000072 0x000074 0x000076 0x000078 0x00007A 0x00007C 0x00007E 0x000080 0x000082 0x000084 0x000086 0x000088 0x00008A 0x00008C 0x00008E 0x000090 0x000092 0x000094 0x000096 0x000098 0x00009A 0x00009C 0x00009E 0x0000A0 0x0000A2 0x0000A40x0000FE AIVT Address 0x000170 0x000172 0x000174 0x000176 0x000178 0x00017A 0x00017C 0x00017E 0x000180 0x000182 0x000184 0x000186 0x000188 0x00018A 0x00018C 0x00018E 0x000190 0x000192 0x000194 0x000196 0x000198 0x00019A 0x00019C 0x00019E 0x0001A0 0x0001A2 0x0001A40x0001FE Interrupt Source DMA4 - DMA Channel 4 T6 - Timer6 T7 - Timer7 SI2C2 - I2C2 Slave Events MI2C2 - I2C2 Master Events T8 - Timer8 T9 - Timer9 INT3 - External Interrupt 3 INT4 - External Interrupt 4 C2RX - ECAN2 Receive Data Ready C2 - ECAN2 Event PWM - PWM Period Match QEI - Position Counter Compare DCIE - DCI Error DCID - DCI Transfer Done DMA5 - DMA Channel 5 Reserved FLTA - MCPWM Fault A FLTB - MCPWM Fault B U1E - UART1 Error U2E - UART2 Error Reserved DMA6 - DMA Channel 6 DMA7 - DMA Channel 7 C1TX - ECAN1 Transmit Data Request C2TX - ECAN2 Transmit Data Request Reserved TABLE 6-2: 0 1 2 3 4 5 6 7 TRAP VECTORS IVT Address 0x000004 0x000006 0x000008 0x00000A 0x00000C 0x00000E 0x000010 0x000012 AIVT Address 0x000084 0x000086 0x000088 0x00008A 0x00008C 0x00008E 0x000090 0x000092 Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error DMA Error Trap Reserved Reserved Vector Number DS70165E-page 90 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 6.3 Interrupt Control and Status Registers The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. The INTTREG register contains the associated interrupt vector number and the new CPU interrupt priority level, which are latched into vector number (VECNUM<6:0>) and Interrupt level (ILR<3:0>) bit fields in the INTTREG register. The new interrupt priority level is the priority of the pending interrupt. The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence that they are listed in Table 6-1. For example, the INT0 (External Interrupt 0) is shown as having vector number 8 and a natural order priority of 0. Thus, the INT0IF bit is found in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP bits in the first position of IPC0 (IPC0<2:0>). Although they are not specifically part of the interrupt control hardware, two of the CPU Control registers contain bits that control interrupt functionality. The CPU STATUS register, SR, contains the IPL<2:0> bits (SR<7:5>). These bits indicate the current CPU interrupt priority level. The user can change the current CPU priority level by writing to the IPL bits. The CORCON register contains the IPL3 bit which, together with IPL<2:0>, also indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. All Interrupt registers are described in Register 6-1 through Register 6-32, in the following pages. dsPIC33F devices implement a total of 30 registers for the interrupt controller: * * * * * * INTCON1 INTCON2 IFS0 through IFS4 IEC0 through IEC4 IPC0 through IPC17 INTTREG Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit as well as the control and status flags for the processor trap sources. The INTCON2 register controls the external interrupt request signal behavior and the use of the Alternate Interrupt Vector Table. The IFS registers maintain all of the interrupt request flags. Each source of interrupt has a Status bit, which is set by the respective peripherals or external signal and is cleared via software. The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 91 dsPIC33F REGISTER 6-1: R-0 OA bit 15 R/W-0(3) IPL2 bit 7 Legend: C = Clear only bit S = Set only bit `1' = Bit is set bit 7-5 R = Readable bit W = Writable bit `0' = Bit is cleared U = Unimplemented bit, read as `0' -n = Value at POR x = Bit is unknown (2) SR: CPU STATUS REGISTER(1) R-0 OB R/C-0 SA R/C-0 SB R-0 OAB R/C-0 SAB R -0 DA R/W-0 DC bit 8 R/W-0(3) IPL1 (2) R/W-0(3) IPL0 (2) R-0 RA R/W-0 N R/W-0 OV R/W-0 Z R/W-0 C bit 0 IPL<2:0>: CPU Interrupt Priority Level Status bits(1) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) For complete register details, see Register 2-1: "SR: CPU STATUS Register". The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1. The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1. Note 1: 2: 3: REGISTER 6-2: U-0 -- bit 15 R/W-0 SATA bit 7 Legend: R = Readable bit 0' = Bit is cleared bit 3 CORCON: CORE CONTROL REGISTER(1) U-0 -- U-0 -- R/W-0 US R/W-0 EDT R-0 R-0 DL<2:0> R-0 bit 8 R/W-0 SATB R/W-1 SATDW R/W-0 ACCSAT R/C-0 IPL3(2) R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 C = Clear only bit W = Writable bit `x = Bit is unknown -n = Value at POR `1' = Bit is set U = Unimplemented bit, read as `0' IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less For complete register details, see Register 2-2: "CORCON: CORE Control Register". The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. Note 1: 2: DS70165E-page 92 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-3: R/W-0 NSTDIS bit 15 R/W-0 SFTACERR bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 DIV0ERR R/W-0 DMACERR R/W-0 MATHERR R/W-0 ADDRERR R/W-0 STKERR R/W-0 OSCFAIL U-0 -- bit 0 INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 OVAERR R/W-0 OVBERR R/W-0 COVAERR R/W-0 COVBERR R/W-0 OVATE R/W-0 OVBTE R/W-0 COVTE bit 8 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled OVAERR: Accumulator A Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator A 0 = Trap was not caused by overflow of Accumulator A OVBERR: Accumulator B Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator B 0 = Trap was not caused by overflow of Accumulator B COVAERR: Accumulator A Catastrophic Overflow Trap Enable bit 1 = Trap was caused by catastrophic overflow of Accumulator A 0 = Trap was not caused by catastrophic overflow of Accumulator A COVBERR: Accumulator B Catastrophic Overflow Trap Enable bit 1 = Trap was caused by catastrophic overflow of Accumulator B 0 = Trap was not caused by catastrophic overflow of Accumulator B OVATE: Accumulator A Overflow Trap Enable bit 1 = Trap overflow of Accumulator A 0 = Trap disabled OVBTE: Accumulator B Overflow Trap Enable bit 1 = Trap overflow of Accumulator B 0 = Trap disabled COVTE: Catastrophic Overflow Trap Enable bit 1 = Trap on catastrophic overflow of Accumulator A or B enabled 0 = Trap disabled SFTACERR: Shift Accumulator Error Status bit 1 = Math error trap was caused by an invalid accumulator shift 0 = Math error trap was not caused by an invalid accumulator shift DIV0ERR: Arithmetic Error Status bit 1 = Math error trap was caused by a divide by zero 0 = Math error trap was not caused by a divide by zero DMACERR: DMA Controller Error Status bit 1 = DMA controller error trap has occurred 0 = DMA controller error trap has not occurred MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 93 dsPIC33F REGISTER 6-3: bit 3 INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred Unimplemented: Read as `0' bit 2 bit 1 bit 0 DS70165E-page 94 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-4: R/W-0 ALTIVT bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 INT4EP R/W-0 INT3EP R/W-0 INT2EP R/W-0 INT1EP INTCON2: INTERRUPT CONTROL REGISTER 2 R-0 DISI U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 INT0EP bit 0 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use alternate vector table 0 = Use standard (default) vector table DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active Unimplemented: Read as `0' INT4EP: External Interrupt 4 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT3EP: External Interrupt 3 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 14 bit 13-5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 95 dsPIC33F REGISTER 6-5: U-0 -- bit 15 R/W-0 T2IF bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 OC2IF R/W-0 IC2IF R/W-0 DMA01IF R/W-0 T1IF R/W-0 OC1IF R/W-0 IC1IF IFS0: INTERRUPT FLAG STATUS REGISTER 0 R/W-0 DMA1IF R/W-0 AD1IF R/W-0 U1TXIF R/W-0 U1RXIF R/W-0 SPI1IF R/W-0 SPI1EIF R/W-0 T3IF bit 8 R/W-0 INT0IF bit 0 Unimplemented: Read as `0' DMA1IF: DMA Channel 1 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI1EIF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DMA0IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 DS70165E-page 96 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-5: bit 2 IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 bit 0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 97 dsPIC33F REGISTER 6-6: R/W-0 U2TXIF bit 15 R/W-0 IC8IF bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 IC7IF R/W-0 AD2IF R/W-0 INT1IF R/W-0 CNIF R/W-0 -- R/W-0 MI2C1IF IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 U2RXIF R/W-0 INT2IF R/W-0 T5IF R/W-0 T4IF R/W-0 OC4IF R/W-0 OC3IF R/W-0 DMA21IF bit 8 R/W-0 SI2C1IF bit 0 U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U2RXIF: UART2 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T5IF: Timer5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T4IF: Timer4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC4IF: Output Compare Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC3IF: Output Compare Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DMA2IF: DMA Channel 2 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC8IF: Input Capture Channel 8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC7IF: Input Capture Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred AD2IF: ADC2 Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 DS70165E-page 98 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-6: bit 3 IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED) CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 99 dsPIC33F REGISTER 6-7: R/W-0 T6IF bit 15 R/W-0 IC5IF bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 IC4IF R/W-0 IC3IF R/W-0 DMA3IF R/W-0 C1IF R/W-0 C1RXIF R/W-0 SPI2IF IFS2: INTERRUPT FLAG STATUS REGISTER 2 R/W-0 DMA4IF U-0 -- R/W-0 OC8IF R/W-0 OC7IF R/W-0 OC6IF R/W-0 OC5IF R/W-0 IC6IF bit 8 R/W-0 SPI2EIF bit 0 T6IF: Timer6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DMA4IF: DMA Channel 4 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' OC8IF: Output Compare Channel 8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC7IF: Output Compare Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC6IF: Output Compare Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC5IF: Output Compare Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC6IF: Input Capture Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC5IF: Input Capture Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC4IF: Input Capture Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC3IF: Input Capture Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DMA3IF: DMA Channel 3 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred C1IF: ECAN1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 DS70165E-page 100 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-7: bit 2 IFS2: INTERRUPT FLAG STATUS REGISTER 2 (CONTINUED) C1RXIF: ECAN1 Receive Data Ready Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 bit 0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 101 dsPIC33F REGISTER 6-8: R/W-0 FLTAIF bit 15 R/W-0 C2RXIF bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 INT4IF R/W-0 INT3IF R/W-0 T9IF R/W-0 T8IF R/W-0 MI2C2IF R/W-0 SI2C2IF IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 -- R/W-0 DMA5IF R/W-0 DCIIF R/W-0 DCIEIF R/W-0 QEIIF R/W-0 PWMIF R/W-0 C2IF bit 8 R/W-0 T7IF bit 0 FLTAIF: PWM Fault A Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' DMA5IF: DMA Channel 5 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DCIIF: DCI Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DCIEIF: DCI Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred QEIIF: QEI Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred PWMIF: PWM Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred C2IF: ECAN2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred C2RXIF: ECAN2 Receive Data Ready Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT4IF: External Interrupt 4 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT3IF: External Interrupt 3 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T9IF: Timer9 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T8IF: Timer8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 DS70165E-page 102 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-8: bit 2 IFS3: INTERRUPT FLAG STATUS REGISTER 3 (CONTINUED) MI2C2IF: I2C2 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C2IF: I2C2 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T7IF: Timer7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 bit 0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 103 dsPIC33F REGISTER 6-9: U-0 -- bit 15 R/W-0 C2TXIF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 C1TXIF R/W-0 DMA7IF R/W-0 DMA6IF U-0 -- R/W-0 U2EIF R/W-0 U1EIF IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 FLTBIF bit 0 Unimplemented: Read as `0' C2TXIF: ECAN2 Transmit Data Request Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred C1TXIF: ECAN1 Transmit Data Request Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DMA7IF: DMA Channel 7 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DMA6IF: DMA Channel 6 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' U2EIF: UART2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred FLTBIF: PWM Fault B Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS70165E-page 104 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-10: U-0 -- bit 15 R/W-0 T2IE bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 OC2IE R/W-0 IC2IE R/W-0 DMA0IE R/W-0 T1IE R/W-0 OC1IE R/W-0 IC1IE IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 R/W-0 R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPI1EIE R/W-0 T3IE bit 8 R/W-0 INT0IE bit 0 DMA1IE Unimplemented: Read as `0' DMA1IE: DMA Channel 1 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled AD1IE: ADC1 Conversion Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPI1IE: SPI1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPI1EIE: SPI1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 105 dsPIC33F REGISTER 6-10: bit 2 IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 bit 0 DS70165E-page 106 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-11: R/W-0 U2TXIE bit 15 R/W-0 IC8IE bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 IC7IE R/W-0 AD2IE R/W-0 INT1IE R/W-0 CNIE R/W-0 -- R/W-0 MI2C1IE IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 INT2IE R/W-0 T5IE R/W-0 T4IE R/W-0 OC4IE R/W-0 OC3IE R/W-0 DMA2IE bit 8 R/W-0 SI2C1IE bit 0 U2RXIE U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled INT2IE: External Interrupt 2 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T5IE: Timer5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T4IE: Timer4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC4IE: Output Compare Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC3IE: Output Compare Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DMA2IE: DMA Channel 2 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC8IE: Input Capture Channel 8 Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC7IE: Input Capture Channel 7 Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred AD2IE: ADC2 Conversion Complete Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 107 dsPIC33F REGISTER 6-11: bit 3 IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 bit 1 bit 0 DS70165E-page 108 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-12: R/W-0 T6IE bit 15 R/W-0 IC5IE bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 IC4IE R/W-0 IC3IE R/W-0 DMA3IE R/W-0 C1IE R/W-0 C1RXIE R/W-0 SPI2IE IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 R/W-0 U-0 -- R/W-0 OC8IE R/W-0 OC7IE R/W-0 OC6IE R/W-0 OC5IE R/W-0 IC6IE bit 8 R/W-0 SPI2EIE bit 0 DMA4IE T6IE: Timer6 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DMA4IE: DMA Channel 4 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' OC8IE: Output Compare Channel 8 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC7IE: Output Compare Channel 7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC6IE: Output Compare Channel 6 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC5IE: Output Compare Channel 5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC6IE: Input Capture Channel 6 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC5IE: Input Capture Channel 5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC4IE: Input Capture Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC3IE: Input Capture Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred C1IE: ECAN1 Event Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 109 dsPIC33F REGISTER 6-12: bit 2 IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 (CONTINUED) C1RXIE: ECAN1 Receive Data Ready Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 bit 0 DS70165E-page 110 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-13: R/W-0 FLTAIE bit 15 R/W-0 C2RXIE bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 INT4IE R/W-0 INT3IE R/W-0 T9IE R/W-0 T8IE R/W-0 MI2C2IE R/W-0 SI2C2IE IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 -- R/W-0 DMA5IE R/W-0 DCIIE R/W-0 DCIEIE R/W-0 QEIIE R/W-0 PWMIE R/W-0 C2IE bit 8 R/W-0 T7IE bit 0 FLTAIE: PWM Fault A Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' DMA5IE: DMA Channel 5 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DCIIE: DCI Event Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DCIEIE: DCI Error Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred QEIIE: QEI Event Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred PWMIE: PWM Error Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred C2IE: ECAN2 Event Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred C2RXIE: ECAN2 Receive Data Ready Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT4IE: External Interrupt 4 Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT3IE: External Interrupt 3 Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T9IE: Timer9 Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T8IE: Timer8 Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 111 dsPIC33F REGISTER 6-13: bit 2 IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 (CONTINUED) MI2C2IE: I2C2 Master Events Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C2IE: I2C2 Slave Events Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T7IE: Timer7 Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 bit 0 DS70165E-page 112 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-14: U-0 -- bit 15 R/W-0 C2TXIE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 C1TXIE R/W-0 DMA7IE R/W-0 DMA6IE U-0 -- R/W-0 U2EIE R/W-0 U1EIE IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 FLTBIE bit 0 Unimplemented: Read as `0' C2TXIE: ECAN2 Transmit Data Request Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred C1TXIE: ECAN1 Transmit Data Request Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DMA7IE: DMA Channel 7 Data Transfer Complete Enable Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DMA6IE: DMA Channel 6 Data Transfer Complete Enable Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' U2EIE: UART2 Error Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred FLTBIE: PWM Fault B Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 113 dsPIC33F REGISTER 6-15: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 IC1IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 INT0IP<2:0> bit 0 IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 R/W-1 R/W-0 T1IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 DS70165E-page 114 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-16: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 IC2IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 DMA0IP<2:0> bit 0 IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 R/W-1 R/W-0 T2IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 OC2IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 115 dsPIC33F REGISTER 6-17: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 SPI1EIP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 T3IP<2:0> bit 0 IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 R/W-1 R/W-0 U1RXIP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SPI1IP<2:0>: SPI1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 DS70165E-page 116 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-18: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 AD1IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 U1TXIP<2:0> bit 0 IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 R/W-0 DMA1IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' DMA1IP<2:0>: DMA Channel 1 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 bit 6-4 bit 3 bit 2-0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 117 dsPIC33F REGISTER 6-19: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 MI2C1IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 SI2C1IP<2:0> bit 0 IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 R/W-1 R/W-0 CNIP<2:0> R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 Unimplemented: Read as `0' CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11-7 bit 6-4 bit 3 bit 2-0 DS70165E-page 118 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-20: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 AD2IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 INT1IP<2:0> bit 0 IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 R/W-1 R/W-0 IC8IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 IC7IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' AD2IP<2:0>: ADC2 Conversion Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 119 dsPIC33F REGISTER 6-21: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 OC3IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 DMA2IP<2:0> bit 0 IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 R/W-1 R/W-0 T4IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 OC4IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' T4IP<2:0>: Timer4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' DMA2IP<2:0>: DMA Channel 2 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 DS70165E-page 120 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-22: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 INT2IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 T5IP<2:0> bit 0 IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 R/W-1 R/W-0 U2TXIP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 U2RXIP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 121 dsPIC33F REGISTER 6-23: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 SPI2IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 SPI2EIP<2:0> bit 0 IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 R/W-1 R/W-0 C1IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 C1RXIP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' C1IP<2:0>: ECAN1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' C1RXIP<2:0>: ECAN1 Receive Data Ready Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SPI2IP<2:0>: SPI2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 DS70165E-page 122 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-24: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 IC3IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 DMA3IP<2:0> bit 0 IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 R/W-1 R/W-0 IC5IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 IC4IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' IC5IP<2:0>: Input Capture Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC4IP<2:0>: Input Capture Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 123 dsPIC33F REGISTER 6-25: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 OC5IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 IC6IP<2:0> bit 0 IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 R/W-1 R/W-0 OC7IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 OC6IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' OC7IP<2:0>: Output Compare Channel 7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC6IP<2:0>: Output Compare Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC5IP<2:0>: Output Compare Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 DS70165E-page 124 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-26: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 R/W-0 OC8IP<2:0> bit 0 IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 R/W-1 R/W-0 T6IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 DMA4IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' T6IP<2:0>: Timer6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' DMA4IP<2:0>: DMA Channel 4 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC8IP<2:0>: Output Compare Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7-3 bit 2-0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 125 dsPIC33F REGISTER 6-27: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 SI2C2IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 T7IP<2:0> bit 0 IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 R/W-1 R/W-0 T8IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 MI2C2IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' T8IP<2:0>: Timer8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' MI2C2IP<2:0>: I2C2 Master Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SI2C2IP<2:0>: I2C2 Slave Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' T7IP<2:0>: Timer7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 DS70165E-page 126 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-28: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 INT3IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 T9IP<2:0> bit 0 IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 R/W-1 R/W-0 C2RXIP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 INT4IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' C2RXIP<2:0>: ECAN2 Receive Data Ready Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' INT4IP<2:0>: External Interrupt 4 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' INT3IP<2:0>: External Interrupt 3 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' T9IP<2:0>: Timer9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 127 dsPIC33F REGISTER 6-29: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 PWMIP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 C2IP<2:0> bit 0 IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 R/W-1 R/W-0 DCIEIP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 QEIIP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' DCIEIP<2:0>: DCI Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' QEIIP<2:0>: QEI Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' PWMIP<2:0>: PWM Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' C2IP<2:0>: ECAN2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 DS70165E-page 128 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-30: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 DMA5IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 DCIIP<2:0> bit 0 IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 R/W-1 R/W-0 FLTAIP<2:0> R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 Unimplemented: Read as `0' FLTAIP<2:0>: PWM Fault A Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' DMA5IP<2:0>: DMA Channel 5 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' DCIIP<2:0>: DCI Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11-7 bit 6-4 bit 3 bit 2-0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 129 dsPIC33F REGISTER 6-31: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 U1EIP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 FLTBIP<2:0> bit 0 IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 R/W-0 U2EIP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' U2EIP<2:0>: UART2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' FLTBIP<2:0>: PWM Fault B Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 bit 6-4 bit 3 bit 2-0 DS70165E-page 130 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 6-32: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 DMA7IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 DMA6IP<2:0> bit 0 IPC17: INTERRUPT PRIORITY CONTROL REGISTER 17 R/W-1 R/W-0 C2TXIP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 C1TXIP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' C2TXIP<2:0>: ECAN2 Transmit Data Request Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' C1TXIP<2:0>: ECAN1 Transmit Data Request Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' DMA7IP<2:0>: DMA Channel 7 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' DMA6IP<2:0>: DMA Channel 6 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 131 dsPIC33F REGISTER 6-33: R-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 R-0 R-0 R-0 VECNUM<6:0> bit 0 R-0 R-0 R-0 INTTREG: INTERRUPT CONTROL AND STATUS REGISTER R/W-0 -- U-0 -- U-0 -- R-0 R-0 ILR<3:0> bit 8 R-0 R-0 Unimplemented: Read as `0' ILR: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 * * * 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 Unimplemented: Read as `0' VECNUM: Vector Number of Pending Interrupt bits 0111111 = Interrupt Vector pending is number 135 * * * 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 bit 7 bit 6-0 DS70165E-page 132 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 6.4 6.4.1 1. 2. Interrupt Setup Procedures INITIALIZATION 6.4.3 TRAP SERVICE ROUTINE To configure an interrupt source: Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source. If multiple priority levels are not desired, the IPCx register control bits for all enabled interrupt sources may be programmed to the same non-zero value. Note: At a device Reset, the IPCx registers are initialized, such that all user interrupt sources are assigned to priority level 4. A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR. 6.4.4 INTERRUPT DISABLE All user interrupts can be disabled using the following procedure: 1. 2. Push the current SR value onto the software stack using the PUSH instruction. Force the CPU to priority level 7 by inclusive ORing the value OEh with SRL. To enable user interrupts, the POP instruction may be used to restore the previous SR value. Note that only user interrupts with a priority level of 7 or less can be disabled. Trap sources (level 8-level 15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. 3. 4. Clear the interrupt flag status bit associated with the peripheral in the associated IFSx register. Enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate IECx register. 6.4.2 INTERRUPT SERVICE ROUTINE The method that is used to declare an ISR and initialize the IVT with the correct vector address will depend on the programming language (i.e., C or assembler) and the language development toolsuite that is used to develop the application. In general, the user must clear the interrupt flag in the appropriate IFSx register for the source of interrupt that the ISR handles. Otherwise, the ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 133 dsPIC33F NOTES: DS70165E-page 134 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 7.0 Note: DIRECT MEMORY ACCESS (DMA) This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). The DMA controller features eight identical data transfer channels. Each channel has its own set of control and status registers. Each DMA channel can be configured to copy data either from buffers stored in dual port DMA RAM to peripheral SFRs, or from peripheral SFRs to buffers in DMA RAM. The DMA controller supports the following features: * Word or byte sized data transfers. * Transfers from peripheral to DMA RAM or DMA RAM to peripheral. * Indirect Addressing of DMA RAM locations with or without automatic post-increment. * Peripheral Indirect Addressing - In some peripherals, the DMA RAM read/write addresses may be partially derived from the peripheral. * One-Shot Block Transfers - Terminating DMA transfer after one block transfer. * Continuous Block Transfers - Reloading DMA RAM buffer start address after every block transfer is complete. * Ping-Pong Mode - Switching between two DMA RAM start addresses between successive block transfers, thereby filling two buffers alternately. * Automatic or manual initiation of block transfers * Each channel can select from 20 possible sources of data sources or destinations. For each DMA channel, a DMA interrupt request is generated when a block transfer is complete. Alternatively, an interrupt can be generated when half of the block has been filled. Direct Memory Access (DMA) is a very efficient mechanism of copying data between peripheral SFRs (e.g., UART Receive register, Input Capture 1 buffer), and buffers or variables stored in RAM, with minimal CPU intervention. The DMA controller can automatically copy entire blocks of data without requiring the user software to read or write the peripheral Special Function Registers (SFRs) every time a peripheral interrupt occurs. The DMA controller uses a dedicated bus for data transfers and therefore, does not steal cycles from the code execution flow of the CPU. To exploit the DMA capability, the corresponding user buffers or variables must be located in DMA RAM. The dsPIC33F peripherals that can utilize DMA are listed in Table 7-1 along with their associated Interrupt Request (IRQ) numbers. TABLE 7-1: PERIPHERALS WITH DMA SUPPORT IRQ Number 0 1 5 2 6 7 8 10 33 11 12 30 31 13 21 60 34 70 55 71 Peripheral INT0 Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2 Timer2 Timer3 SPI1 SPI2 UART1 Reception UART1 Transmission UART2 Reception UART2 Transmission ADC1 ADC2 DCI ECAN1 Reception ECAN1 Transmission ECAN2 Reception ECAN2 Transmission (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 135 dsPIC33F FIGURE 7-1: TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS Peripheral Indirect Address DMA Controller DMA Control SRAM DMA RAM PORT 1 PORT 2 DMA Channels DMA Ready Peripheral 3 CPU DMA SRAM X-Bus DMA DS Bus CPU Peripheral DS Bus CPU DMA CPU DMA CPU Non-DMA Ready Peripheral DMA Ready Peripheral 1 DMA Ready Peripheral 2 Note: CPU and DMA address buses are not shown for clarity. 7.1 DMAC Registers Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7) contains the following registers: * A 16-bit DMA Channel Control register (DMAxCON) * A 16-bit DMA Channel IRQ Select register (DMAxREQ) * A 16-bit DMA RAM Primary Start Address register (DMAxSTA) * A 16-bit DMA RAM Secondary Start Address register (DMAxSTB) * A 16-bit DMA Peripheral Address register (DMAxPAD) * A 10-bit DMA Transfer Count register (DMAxCNT) An additional pair of status registers, DMACS0 and DMACS1, are common to all DMAC channels. DMACS0 contains the DMA RAM and SFR write collision flags, XWCOLx and PWCOLx, respectively. DMACS1 indicates DMA channel and Ping-Pong mode status. The DMAxCON, DMAxREQ, DMAxPAD and DMAxCNT are all conventional read/write registers. Reads of DMAxSTA or DMAxSTB will read the contents of the DMA RAM Address register. Writes to DMAxSTA or DMAxSTB write to the registers. This allows the user to determine the DMA buffer pointer value (address) at any time. The interrupt flags (DMAxIF) are located in an IFSx register in the interrupt controller. The corresponding interrupt enable control bits (DMAxIE) are located in an IECx register in the interrupt controller, and the corresponding interrupt priority control bits (DMAxIP) are located in an IPCx register in the interrupt controller. 7.2 DMAC Operating Modes Each DMA channel has its own status and control register (DMAxCON) that is used to configure the channel to support the following operating modes: * Word or byte size data transfers * Peripheral to DMA RAM or DMA RAM to peripheral transfers * Post-increment or static DMA RAM address * One-shot or continuous block transfers * Auto-switch between two start addresses after each transfer complete (Ping-Pong mode) * Force a single DMA transfer (Manual mode) Each DMA channel can be independently configured to: * Select from one of 20 DMA request sources * Manually enable or disable the DMA channel * Interrupt the CPU when the transfer is half or fully complete DMA channel interrupts are routed to the interrupt controller module and enabled through associated enable flags. The channel DMA RAM and peripheral write collision Faults are combined into a single DMAC error trap (Level 10) and are not maskable. Each channel has DMA RAM write collision (XWCOLx) and peripheral DS70165E-page 136 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F write collision (PWCOLx) status bits in a DMAC Status register (DMACS0) to allow the DMAC error trap handler to determine the source of the Fault condition. Any DMA channel can be configured to operate in Peripheral Indirect Addressing mode by setting the AMODE<1:0> bits to `10'. In this mode, the DMA RAM source or destination address is partially derived from the peripheral as well as the DMA Address registers. Each peripheral module has a pre-assigned peripheral indirect address which is logically ORed with the DMA Start Address register to obtain the effective DMA RAM address. The DMA RAM Start Address register value must be aligned to a power-of-two boundary. Note: Only the ECAN and ADC modules can use Peripheral Indirect Addressing 7.2.1 BYTE OR WORD TRANSFER Each DMA channel can be configured to transfer words or bytes. As usual, words can only be moved to and from aligned (even) addresses. Bytes can be moved to or from any (legal) address. If the SIZE bit (DMAxCON<14>) is clear, word sized data is transferred. The LSb of the DMA RAM Address register (DMAxSTA or DMAxSTB) is ignored. If Post-Increment Addressing mode is enabled, the DMA RAM Address register is incremented by 2 after every word transfer. If the SIZE bit is set, byte sized data is transferred. If Post-Increment Addressing is enabled, the DMA RAM Address register is incremented by 1 after every byte transfer. Note: DMAxCNT value is independent of data transfer size (byte/word). If an address offset is required, a 1-bit left shift of the counter is required to generate the correct offset for (aligned) word transfers. 7.2.3 DMA TRANSFER DIRECTION Each DMA channel can be configured to transfer data from a peripheral to DMA RAM, or from DMA RAM to a peripheral. If the DIR bit (DMAxCON<13>) is clear, the reads occur from a peripheral SFR (using the DMA Peripheral Address register, DMAxPAD) and the writes are directed to the DMA RAM (using the DMA RAM Address register). If the DIR bit (DMAxCON<13>) is set, the reads occur from the DMA RAM (using the DMA RAM Address register) and the writes are directed to the peripheral (using the DMA Peripheral Address register, DMAxPAD). 7.2.2 ADDRESSING MODES The DMAC supports Register Indirect and Register Indirect Post-Increment Addressing modes for DMA RAM addresses (source or destination). Each channel can select the DMA RAM Addressing mode independently. The Peripheral SFR is always accessed using Register Indirect Addressing. If the AMODE<1:0> bits (DMAxCON<5:4>) are set to `01', Register Indirect Addressing without Post-Increment is used, which implies that the DMA RAM address remains constant. If the AMODE<1:0> bits are clear, DMA RAM is accessed using Register Indirect Addressing with Post-Increment, which means the DMA RAM address will be incremented after every access 7.2.4 NULL DATA PERIPHERAL WRITE MODE If the NULLW bit (DMAxCON<11>) is set, a null data write to the peripheral SFR is performed in addition to a data transfer from the peripheral SFR to DMA RAM (assuming the DIR bit is clear). This mode is most useful in applications in which sequential reception of data is required without any data transmission (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 137 dsPIC33F 7.2.5 CONTINUOUS OR ONE-SHOT OPERATION Each DMA channel can be configured for One-Shot or Continuous mode operation. If MODE<0> (DMAxCON<0>) is clear, the channel operates in Continuous mode. When all data has been moved (i.e., buffer end has been detected), the channel is automatically reconfigured for subsequent use. During the last data transfer, the next Effective Address generated will be the original start address (from the selected DMAxSTA or DMAxSTB register). If the HALF bit (DMAxCON<12>) is clear, the transfer complete interrupt flag (DMAxIF) is set. If the HALF bit is set, DMAxIF will not be set at this time and the channel will remain enabled. If MODE<0> is set, the channel operates in One-Shot mode. When all data has been moved (i.e., buffer end has been detected), the channel is automatically disabled. During the last data transfer, no new Effective Address is generated and the DMA RAM Address register retains the last DMA RAM address that was accessed. If the HALF bit is clear, the DMAxIF bit is set. If the HALF bit is set, the DMAxIF will not be set at this time and the channel is automatically disabled. This mode provides the user a straightforward method of initiating a block transfer. For example, using Manual mode to transfer the first data element into a serial peripheral allows subsequent data within the buffer to be moved automatically by the DMAC using a `transmit buffer empty' DMA request. 7.2.8 DMA REQUEST SOURCE SELECTION Each DMA channel can select between one of 128 interrupt sources to be a DMA request for that channel, based on the contents of the IRQSEL<6:0> bits (DMAxREQ<6:0>). The available interrupt sources are device dependent. Please refer to Table 7-1 for IRQ numbers associated with each of the interrupt sources that can generate a DMA transfer. 7.3 DMA Interrupts and Traps 7.2.6 PING-PONG MODE When the MODE<1> bit (DMAxCON<1>) is set by the user, Ping-Pong mode is enabled. In this mode, successive block transfers alternately select DMAxSTA and DMAxSTB as the DMA RAM start address. In this way, a single DMA channel can be used to support two buffers of the same length in DMA RAM. Using this technique maximizes data throughput by allowing the CPU time to process one buffer while the other is being loaded. Each DMA channel can generate an independent `block transfer complete' (HALF = 0) or `half block transfer complete' (HALF = 1) interrupt. Every DMA channel has its own interrupt vector and therefore, does not use the interrupt vector of the peripheral to which it is assigned. If a peripheral contains multi-word buffers, the buffering function must be disabled in the peripheral in order to use DMA. DMA interrupt requests are only generated by data transfers and not by peripheral error conditions. The DMA controller can also react to peripheral and DMA RAM write collision error conditions through a nonmaskable CPU trap event. A DMA error trap is generated in either of the following Fault conditions: * DMA RAM data write collision between the CPU and a peripheral - This condition occurs when the CPU and a peripheral attempt to write to the same DMA RAM address simultaneously * Peripheral SFR data write collision between the CPU and the DMA controller - This condition occurs when the CPU and the DMA controller attempt to write to the same peripheral SFR simultaneously The channel DMA RAM and peripheral write collision Faults are combined into a single DMAC error trap (Level 10) and are nonmaskable. Each channel has DMA RAM Write Collision (XWCOLx) and Peripheral Write Collision (PWCOLx) status bits in the DMAC Status register (DMACS) to allow the DMAC error trap handler to determine the source of the Fault condition. 7.2.7 MANUAL TRANSFER MODE A manual DMA request can be created by setting the FORCE bit (DMAxREQ<15>) in software. If already enabled, the corresponding DMA channel executes a single data element transfer rather than a block transfer The FORCE bit is cleared by hardware when the forced DMA transfer is complete and cannot be cleared by the user. Any attempt to set this bit prior to completion of a DMA request that is underway will have no effect. The manual DMA transfer function is a one-time event. The DMA channel always reverts to normal operation (i.e., based on hardware DMA requests) after a forced (manual) transfer. DS70165E-page 138 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 7.4 DMA Initialization Example The following is a DMA initialization example: EXAMPLE 7-1: DMACS0 = DMA SAMPLE INITIALIZATION METHOD 0; // Clear all DMA controller status bits to a known state // Set up DMA Channel 0: Word mode, Read from Peripheral & Write to DMA; Interrupt when all the data has been moved; Indirect with post-increment; Continuous mode with Ping-Pong Disabled DMA0CON = 0x0000; //Automatic DMA transfer initiation by DMA request; DMA Peripheral IRQ Number set up for ADC1 DMA0REQ = 0x000D; // Set up offset into DMA RAM so that the buffer that collects ADC result data starts at the base of DMA RAM DMA0STA = 0x0000; // DMA0PAD should be loaded with the address of the ADC conversion result register DMA0PAD = (volatile unsigned int) &ADC1BUF0; // DMA transfer of 256 words of data DMA0CNT = 0x0100 ; //Clear the DMA0 Interrupt Flag IFS0bits.DMA0IF = 0; //Enable DMA0 Interrupts IEC0bits.DMA0IE = 1; //Enable the DMA0 Channel DMA0CONbits.CHEN = 1; (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 139 dsPIC33F REGISTER 7-1: R/W-0 CHEN bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 DMAxCON: DMA CHANNEL x CONTROL REGISTER R/W-0 SIZE R/W-0 DIR R/W-0 HALF R/W-0 NULLW U-0 -- U-0 -- U-0 -- bit 8 R/W-0 bit 0 AMODE<1:0> MODE<1:0> CHEN: Channel Enable bit 1 = Channel enabled 0 = Channel disabled SIZE: Data Transfer Size bit 1 = Byte 0 = Word DIR: Transfer Direction bit (source/destination bus select) 1 = Read from DMA RAM address, write to peripheral address 0 = Read from peripheral address, write to DMA RAM address HALF: Early Block Transfer Complete Interrupt Select bit 1 = Initiate block transfer complete interrupt when half of the data has been moved 0 = Initiate block transfer complete interrupt when all of the data has been moved NULLW: Null Data Peripheral Write Mode Select bit 1 = Null data write to peripheral in addition to DMA RAM write (DIR bit must also be clear) 0 = Normal operation Unimplemented: Read as `0' AMODE<1:0>: DMA Channel Operating Mode Select bits 11 = Reserved (will act as Peripheral Indirect Addressing mode) 10 = Peripheral Indirect Addressing mode 01 = Register Indirect without Post-Increment mode 00 = Register Indirect with Post-Increment mode Unimplemented: Read as `0' MODE<1:0>: DMA Channel Operating Mode Select bits 11 = One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer) 10 = Continuous, Ping-Pong modes enabled 01 = One-Shot, Ping-Pong modes disabled 00 = Continuous, Ping-Pong modes disabled bit 14 bit 13 bit 12 bit 11 bit 10-6 bit 5-4 bit 3-2 bit 1-0 DS70165E-page 140 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 7-2: R/W-0 FORCE(1) bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 IRQSEL6 (2) DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 IRQSEL5 (2) R/W-0 IRQSEL4 (2) U-0 IRQSEL3 (2) U-0 IRQSEL2 (2) R/W-0 IRQSEL1 (2) R/W-0 IRQSEL0(2) bit 0 FORCE: Force DMA Transfer bit(1) 1 = Force a single DMA transfer (Manual mode) 0 = Automatic DMA transfer initiation by DMA request Unimplemented: Read as `0' IRQSEL<6:0>: DMA Peripheral IRQ Number Select bits(2) 0000000-1111111 = DMAIRQ0-DMAIRQ127 selected to be Channel DMAREQ The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced DMA transfer is complete. Please see Table 6-1 for a complete listing of IRQ numbers for all interrupt sources. bit 14-7 bit 6-0 Note 1: 2: (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 141 dsPIC33F REGISTER 7-3: R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMAxSTA: DMA CHANNEL x RAM START ADDRESS REGISTER A(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 STA<15:8> STA<7:0> STA<15:0>: Primary DMA RAM Start Address bits (source or destination) A read of this address register will return the current contents of the DMA RAM Address register, not the contents written to STA<15:0>. If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. REGISTER 7-4: R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 Note 1: DMAxSTB: DMA CHANNEL x RAM START ADDRESS REGISTER B(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 STB<15:8> STB<7:0> W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown STB<15:0>: Secondary DMA RAM Start Address bits (source or destination) A read of this address register will return the current contents of the DMA RAM Address register, not the contents written to STB<15:0>. If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. DS70165E-page 142 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 7-5: R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 Note 1: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 PAD<15:8> PAD<7:0> PAD<15:0>: Peripheral Address Register bits If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. REGISTER 7-6: U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9-0 Note 1: 2: DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CNT<9:8>(2) bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 CNT<7:0> W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' CNT<9:0>: DMA Transfer Count Register bits(2) If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. Number of DMA transfers = CNT<9:0> + 1. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 143 dsPIC33F REGISTER 7-7: R/C-0 PWCOL7 bit 15 R/C-0 XWCOL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/C-0 XWCOL6 R/C-0 XWCOL5 R/C-0 XWCOL4 R/C-0 XWCOL3 R/C-0 XWCOL2 R/C-0 XWCOL1 DMACS0: DMA CONTROLLER STATUS REGISTER 0 R/C-0 PWCOL6 R/C-0 PWCOL5 R/C-0 PWCOL4 R/C-0 PWCOL3 R/C-0 PWCOL2 R/C-0 PWCOL1 R/C-0 PWCOL0 bit 8 R/C-0 XWCOL0 bit 0 PWCOL7: Channel 7 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected PWCOL6: Channel 6 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected PWCOL5: Channel 5 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected PWCOL4: Channel 4 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected PWCOL3: Channel 3 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected PWCOL2: Channel 2 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected PWCOL1: Channel 1 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected PWCOL0: Channel 0 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected XWCOL7: Channel 7 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected XWCOL6: Channel 6 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected XWCOL5: Channel 5 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected XWCOL4: Channel 4 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 DS70165E-page 144 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 7-7: bit 3 DMACS0: DMA CONTROLLER STATUS REGISTER 0 (CONTINUED) XWCOL3: Channel 3 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected XWCOL2: Channel 2 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 145 dsPIC33F REGISTER 7-8: U-0 -- bit 15 R-0 PPST7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 PPST6 R-0 PPST5 R-0 PPST4 R-0 PPST3 R-0 PPST2 R-0 PPST1 R-0 PPST0 bit 0 DMACS1: DMA CONTROLLER STATUS REGISTER 1 U-0 -- U-0 -- U-0 -- R-1 R-1 R-1 R-1 bit 8 LSTCH<3:0> Unimplemented: Read as `0' LSTCH<3:0>: Last DMA Channel Active bits 1111 = No DMA transfer has occurred since system Reset 1110-1000 = Reserved 0111 = Last data transfer was by DMA Channel 7 0110 = Last data transfer was by DMA Channel 6 0101 = Last data transfer was by DMA Channel 5 0100 = Last data transfer was by DMA Channel 4 0011 = Last data transfer was by DMA Channel 3 0010 = Last data transfer was by DMA Channel 2 0001 = Last data transfer was by DMA Channel 1 0000 = Last data transfer was by DMA Channel 0 PPST7: Channel 7 Ping-Pong Mode Status Flag bit 1 = DMA7STB register selected 0 = DMA7STA register selected PPST6: Channel 6 Ping-Pong Mode Status Flag bit 1 = DMA6STB register selected 0 = DMA6STA register selected PPST5: Channel 5 Ping-Pong Mode Status Flag bit 1 = DMA5STB register selected 0 = DMA5STA register selected PPST4: Channel 4 Ping-Pong Mode Status Flag bit 1 = DMA4STB register selected 0 = DMA4STA register selected PPST3: Channel 3 Ping-Pong Mode Status Flag bit 1 = DMA3STB register selected 0 = DMA3STA register selected PPST2: Channel 2 Ping-Pong Mode Status Flag bit 1 = DMA2STB register selected 0 = DMA2STA register selected PPST1: Channel 1 Ping-Pong Mode Status Flag bit 1 = DMA1STB register selected 0 = DMA1STA register selected PPST0: Channel 0 Ping-Pong Mode Status Flag bit 1 = DMA0STB register selected 0 = DMA0STA register selected bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS70165E-page 146 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 7-9: R-0 bit 15 R-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 0 DSADR: MOST RECENT DMA RAM ADDRESS R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 8 DSADR<15:8> DSADR<7:0> DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 147 dsPIC33F NOTES: DS70165E-page 148 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 8.0 Note: OSCILLATOR CONFIGURATION This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). The dsPIC33F oscillator system provides: * Various external and internal oscillator options as clock sources * An on-chip PLL to scale the internal operating frequency to the required system clock frequency * The internal FRC oscillator can also be used with the PLL, thereby allowing full-speed operation without any external clock generation hardware * Clock switching between various clock sources * Programmable clock postscaler for system power savings * A Fail-Safe Clock Monitor (FSCM) that detects clock failure and takes fail-safe measures * A Clock Control register (OSCCON) * Nonvolatile Configuration bits for main oscillator selection. A simplified diagram of the oscillator system is shown in Figure 8-1. FIGURE 8-1: dsPIC33F OSCILLATOR SYSTEM DIAGRAM Primary Oscillator OSC2 dsPIC33F XT, HS, EC XTPLL, HSPLL, ECPLL, FRCPLL DOZE<2:0> /DOZE OSC1 PLL CPU /FRCDIIV FRC Oscillator FRC, FRCDIVN Peripherals FRCDIV<2:0> Divide By 16 LPRC Oscillator Secondary Oscillator SOSCO SOSCEN Enable Oscillator SOSC LPRC FRCDIV16 SOSCI Clock Control Logic Fail-Safe Clock Monitor WDT, PWRT Clock Source Option for other Modules (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 149 dsPIC33F 8.1 CPU Clocking System There are seven system clock options provided by the dsPIC33F: * * * * * * * FRC Oscillator FRC Oscillator with PLL Primary (XT, HS or EC) Oscillator Primary Oscillator with PLL Secondary (LP) Oscillator LPRC Oscillator FRC Oscillator with postscaler (FOSC<1:0>), select the oscillator source that is used at a Power-on Reset. The FRC primary oscillator is the default (unprogrammed) selection. The Configuration bits allow users to choose between twelve different clock modes, shown in Table 8-1. The output of the oscillator (or the output of the PLL if a PLL mode has been selected) FOSC is divided by 2 to generate the device instruction clock (FCY). FCY defines the operating speed of the device, and speeds up to 40 MHz are supported by the dsPIC33F architecture. Instruction execution speed or device operating frequency, FCY, is given by: 8.1.1 SYSTEM CLOCK SOURCES The FRC (Fast RC) internal oscillator runs at a nominal frequency of 7.37 MHz. The user software can tune the FRC frequency. User software can optionally specify a factor (ranging from 1:2 to 1:256) by which the FRC clock frequency is divided. This factor is selected using the FRCDIV<2:0> (CLKDIV<10:8>) bits. The primary oscillator can use one of the following as its clock source: 1. XT (Crystal): Crystals and ceramic resonators in the range of 3 MHz to 10 MHz. The crystal is connected to the OSC1 and OSC2 pins. HS (High-Speed Crystal): Crystals in the range of 10 MHz to 40 MHz. The crystal is connected to the OSC1 and OSC2 pins. EC (External Clock): External clock signal in the range of 0.8 MHz to 64 MHz. The external clock signal is directly applied to the OSC1 pin. EQUATION 8-1: DEVICE OPERATING FREQUENCY FCY = FOSC/2 8.1.3 PLL CONFIGURATION 2. The primary oscillator and internal FRC oscillator can optionally use an on-chip PLL to obtain higher speeds of operation. The PLL provides a significant amount of flexibility in selecting the device operating speed. A block diagram of the PLL is shown in Figure 8-2. The output of the primary oscillator or FRC, denoted as `FIN', is divided down by a prescale factor (N1) of 2, 3, ... or 33 before being provided to the PLL's Voltage Controlled Oscillator (VCO). The input to the VCO must be selected to be in the range of 0.8 MHz to 8 MHz. Since the minimum prescale factor is 2, this implies that FIN must be chosen to be in the range of 1.6 MHz to 16 MHz. The prescale factor `N1' is selected using the PLLPRE<4:0> bits (CLKDIV<4:0>). The PLL Feedback Divisor, selected using the PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor `M', by which the input to the VCO is multiplied. This factor must be selected such that the resulting VCO output frequency is in the range of 100 MHz to 200 MHz. The VCO output is further divided by a postscale factor `N2'. This factor is selected using the PLLPOST<1:0> bits (CLKDIV<7:6>). `N2' can be either 2, 4 or 8, and must be selected such that the PLL output frequency (FOSC) is in the range of 12.5 MHz to 80 MHz, which generates device operating speeds of 6.25-40 MIPS. For a primary oscillator or FRC oscillator, output `FIN', the PLL output `FOSC' is given by: 3. The secondary (LP) oscillator is designed for low power and uses a 32.768 kHz crystal or ceramic resonator. The LP oscillator uses the SOSCI and SOSCO pins. The LPRC (Low-Power RC) internal oscIllator runs at a nominal frequency of 32.768 kHz. It is also used as a reference clock by the Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The clock signals generated by the FRC and primary oscillators can be optionally applied to an on-chip Phase Locked Loop (PLL) to provide a wide range of output frequencies for device operation. PLL configuration is described in Section 8.1.3 "PLL Configuration". 8.1.2 SYSTEM CLOCK SELECTION The oscillator source that is used at a device Power-on Reset event is selected using Configuration bit settings. The oscillator Configuration bit settings are located in the Configuration registers in the program memory. (Refer to Section 23.1 "Configuration Bits" for further details.) The Initial Oscillator Selection Configuration bits, FNOSC<2:0> (FOSCSEL<2:0>), and the Primary Oscillator Mode Select Configuration bits, POSCMD<1:0> EQUATION 8-2: FOSC CALCULATION M ( N1*N2 ) FOSC = FIN* DS70165E-page 150 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F For example, suppose a 10 MHz crystal is being used, with "XT with PLL" being the selected oscillator mode. If PLLPRE<4:0> = 0, then N1 = 2. This yields a VCO input of 10/2 = 5 MHz, which is within the acceptable range of 0.8-8 MHz. If PLLDIV<8:0> = 0x1E, then M = 32. This yields a VCO output of 5 x 32 = 160 MHz, which is within the 100-200 MHz ranged needed. If PLLPOST<1:0> = 0, then N2 = 2. This provides a Fosc of 160/2 = 80 MHz. The resultant device operating speed is 80/2 = 40 MIPS. EQUATION 8-3: XT WITH PLL MODE EXAMPLE FCY = FOSC 1 10000000*32 = = 40 MIPS 2 2 2*2 ( ) FIGURE 8-2: dsPIC33F PLL BLOCK DIAGRAM 0.8-8.0 MHz Here Source (Crystal, External Clock or Internal RC) 100-200 MHz Here 12.5-80 MHz Here PLLPRE X VCO PLLDIV PLLPOST FOSC 1.6-16.0 MHz Here Divide by 2-33 Divide by 2-513 Divide by 2, 4, 8 TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Source Internal Internal Internal Secondary Primary Primary Primary Primary Primary Primary Internal Internal POSCMD<1:0> 11 11 11 11 10 01 00 10 01 00 11 11 FNOSC<2:0> 111 110 101 100 011 011 011 010 010 010 001 000 1 1 1 1 Note 1, 2 1 1 1 Oscillator Mode Fast RC Oscillator with Divide-by-N (FRCDIVN) Fast RC Oscillator with Divide-by-16 (FRCDIV16) Low-Power RC Oscillator (LPRC) Secondary (Timer1) Oscillator (SOSC) Primary Oscillator (HS) with PLL (HSPLL) Primary Oscillator (XT) with PLL (XTPLL) Primary Oscillator (EC) with PLL (ECPLL) Primary Oscillator (HS) Primary Oscillator (XT) Primary Oscillator (EC) Fast RC Oscillator with PLL (FRCPLL) Fast RC Oscillator (FRC) Note 1: 2: OSC2 pin function is determined by the OSCIOFNC Configuration bit. This is the default oscillator mode for an unprogrammed (erased) device. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 151 dsPIC33F REGISTER 8-1: U-0 -- bit 15 R/W-0 CLKLOCK bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 y = Value set from Configuration bits on POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R-0 LOCK U-0 -- R/C-0 CF U-0 -- R/W-0 LPOSCEN OSCCON: OSCILLATOR CONTROL REGISTER R-0 R-0 COSC<2:0> R-0 U-0 -- R/W-y R/W-y NOSC<2:0> bit 8 R/W-0 OSWEN bit 0 R/W-y Unimplemented: Read as `0' COSC<2:0>: Current Oscillator Selection bits (read-only) 000 = Fast RC oscillator (FRC) 001 = Fast RC oscillator (FRC) with PLL 010 = Primary oscillator (XT, HS, EC) 011 = Primary oscillator (XT, HS, EC) with PLL 100 = Secondary oscillator (SOSC) 101 = Low-Power RC oscillator (LPRC) 110 = Fast RC oscillator (FRC) with Divide-by-16 111 = Fast RC oscillator (FRC) with Divide-by-n Unimplemented: Read as `0' NOSC<2:0>: New Oscillator Selection bits 000 = Fast RC oscillator (FRC) 001 = Fast RC oscillator (FRC) with PLL 010 = Primary oscillator (XT, HS, EC) 011 = Primary oscillator (XT, HS, EC) with PLL 100 = Secondary oscillator (SOSC) 101 = Low-Power RC oscillator (LPRC) 110 = Fast RC oscillator (FRC) with Divide-by-16 111 = Fast RC oscillator (FRC) with Divide-by-n CLKLOCK: Clock Lock Enable bit 1 = If (FCKSM1 = 1), then clock and PLL configurations are locked. If (FCKSM1 = 0), then clock and PLL configurations may be modified. 0 = Clock and PLL selections are not locked, configurations may be modified Unimplemented: Read as `0' LOCK: PLL Lock Status bit (read-only) 1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied 0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled Unimplemented: Read as `0' CF: Clock Fail Detect bit (read/clear by application) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure Unimplemented: Read as `0' LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete bit 11 bit 10-8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS70165E-page 152 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 8-2: R/W-0 ROI bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 y = Value set from Configuration bits on POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 U-0 -- R/W-0 R/W-0 R/W-0 PLLPRE<4:0> bit 0 R/W-0 CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-0 DOZE<2:0> R/W-0 R/W-0 DOZEN(1) R/W-1 R/W-0 FRCDIV<2:0> bit 8 R/W-0 R/W-0 PLLPOST<1:0> ROI: Recover on Interrupt bit 1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1 0 = Interrupts have no effect on the DOZEN bit DOZE<2:0>: Processor Clock Reduction Select bits(3) 000 = FCY/1 (default) 001 = FCY/2 010 = FCY/4 011 = FCY/8 100 = FCY/16 101 = FCY/32 110 = FCY/64 111 = FCY/128 DOZEN: DOZE Mode Enable bit(1) 1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = Processor clock/peripheral clock ratio forced to 1:1 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits 000 = FRC divide by 1 001 = FRC divide by 2 010 = FRC divide by 4 011 = FRC divide by 8 (default) 100 = FRC divide by 16 101 = FRC divide by 32 110 = FRC divide by 64 111 = FRC divide by 256 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as `N2', PLL postscaler)(2) 00 = Output/2 01 = Output/4 10 = Reserved (defaults to output/4) 11 = Output/8 Unimplemented: Read as `0' PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as `N1', PLL prescaler) 00000 = Input/2 00001 = Input/3 *** 11111 = Input/33 This bit is cleared when the ROI bit is set and an interrupt occurs. bit 14-12 bit 11 bit 10-8 bit 7-6 bit 5 bit 4-0 Note 1: (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 153 dsPIC33F REGISTER 8-3: U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 PLLFBD: PLL FEEDBACK DIVISOR REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0(1) PLLDIV<8> bit 8 R/W-0 bit 0 PLLDIV<7:0> Unimplemented: Read as `0' PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as `M', PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 * * * 111111111 = 513 DS70165E-page 154 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 8-4: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 TUN5 R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 TUN0 bit 0 Unimplemented: Read as `0' TUN<5:0>: FRC Oscillator Tuning bits 011111 = Center frequency + 11.625% 011110 = Center frequency + 11.25% (8.23 MHz) * * * 000001 = Center frequency + 0.375% (7.40 MHz) 000000 = Center frequency (7.37 MHz nominal) 111111 = Center frequency - 0.375% (7.345 MHz) * * * 100001 = Center frequency - 11.625% (6.52 MHz) 100000 = Center frequency - 12% (6.49 MHz) (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 155 dsPIC33F 8.2 Clock Switching Operation Applications are free to switch between any of the four clock sources (Primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects that could result from this flexibility, dsPIC33F devices have a safeguard lock built into the switch process. Note: Primary Oscillator mode has three different submodes (XT, HS and EC) which are determined by the POSCMD<1:0> Configuration bits. While an application can switch to and from Primary Oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device. Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSC status bits with the new value of the NOSC control bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and the CF (OSCCON<3>) status bits are cleared. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware waits until the Oscillator Start-up Timer (OST) expires. If the new source is using the PLL, the hardware waits until a PLL lock is detected (LOCK = 1). The hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSC bit values are transferred to the COSC status bits. The old clock source is turned off at this time, with the exception of LPRC (if WDT or FSCM are enabled) or LP (if LPOSCEN remains set). Note 1: The processor continues to execute code throughout the clock switching sequence. Timing sensitive code should not be executed during this time. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 2. 3. 8.2.1 ENABLING CLOCK SWITCHING 4. To enable clock switching, the FCKSM1 Configuration bit in the Configuration register must be programmed to `0'. (Refer to Section 23.1 "Configuration Bits" for further details.) If the FCKSM1 Configuration bit is unprogrammed (`1'), the clock switching function and Fail-Safe Clock Monitor function are disabled. This is the default setting. The NOSC control bits (OSCCON<10:8>) do not control the clock selection when clock switching is disabled. However, the COSC bits (OSCCON<14:12>) reflect the clock source selected by the FNOSC Configuration bits. The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled. It is held at `0' at all times. 5. 6. 8.2.2 OSCILLATOR SWITCHING SEQUENCE At a minimum, performing a clock switch requires this basic sequence: 1. If desired, read the COSC bits (OSCCON<14:12>) to determine the current oscillator source. Perform the unlock sequence to allow a write to the OSCCON register high byte. Write the appropriate value to the NOSC control bits (OSCCON<10:8>) for the new oscillator source. Perform the unlock sequence to allow a write to the OSCCON register low byte. Set the OSWEN bit to initiate the oscillator switch. 8.3 Fail-Safe Clock Monitor (FSCM) 2. 3. The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by programming. If the FSCM function is enabled, the LPRC internal oscillator runs at all times (except during Sleep mode) and is not subject to control by the Watchdog Timer. In the event of an oscillator failure, the FSCM generates a clock failure trap event and switches the system clock over to the FRC oscillator. Then the application program can either attempt to restart the oscillator or execute a controlled shutdown. The trap can be treated as a warm Reset by simply loading the Reset address into the oscillator fail trap vector. If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. 4. 5. DS70165E-page 156 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 9.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). operation and halts all code execution. Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. The assembly syntax of the PWRSAV instruction is shown in Example 9-1. Note: SLEEP_MODE and IDLE_MODE are constants defined in the assembler include file for the selected device. The dsPIC33F devices provide the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. dsPIC33F devices can manage power consumption in four different ways: * * * * Clock frequency Instruction-based Sleep and Idle modes Software-controlled Doze mode Selective peripheral control in software Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to "wake-up". 9.2.1 SLEEP MODE Sleep mode has these features: * The system clock source is shut down. If an on-chip oscillator is used, it is turned off. * The device current consumption is reduced to a minimum, provided that no I/O pin is sourcing current. * The Fail-Safe Clock Monitor does not operate during Sleep mode since the system clock source is disabled. * The LPRC clock continues to run in Sleep mode if the WDT is enabled. * The WDT, if enabled, is automatically cleared prior to entering Sleep mode. * Some device features or peripherals may continue to operate in Sleep mode. This includes items such as the input change notification on the I/O ports, or peripherals that use an external clock input. Any peripheral that requires the system clock source for its operation is disabled in Sleep mode. The device will wake-up from Sleep mode on any of the these events: * Any interrupt source that is individually enabled. * Any form of device Reset. * A WDT time-out. On wake-up from Sleep, the processor restarts with the same clock source that was active when Sleep mode was entered. Combinations of these methods can be used to selectively tailor an application's power consumption while still maintaining critical application features, such as timing-sensitive communications. 9.1 Clock Frequency and Clock Switching dsPIC33F devices allow a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSC bits (OSCCON<10:8>). The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section 8.0 "Oscillator Configuration". 9.2 Instruction-Based Power-Saving Modes dsPIC33F devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX ; Put the device into SLEEP mode ; Put the device into IDLE mode PWRSAV #SLEEP_MODE PWRSAV #IDLE_MODE (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 157 dsPIC33F 9.2.2 IDLE MODE Idle mode has these features: * The CPU stops executing instructions. * The WDT is automatically cleared. * The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 "Peripheral Module Disable"). * If the WDT or FSCM is enabled, the LPRC also remains active. The device will wake from Idle mode on any of these events: * Any interrupt that is individually enabled. * Any device Reset. * A WDT time-out. On wake-up from Idle, the clock is reapplied to the CPU and instruction execution begins immediately, starting with the instruction following the PWRSAV instruction, or the first instruction in the ISR. Doze mode is enabled by setting the DOZEN bit (CLKDIV<11>). The ratio between peripheral and core clock speed is determined by the DOZE<2:0> bits (CLKDIV<14:12>). There are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default setting. It is also possible to use Doze mode to selectively reduce power consumption in event-driven applications. This allows clock-sensitive functions, such as synchronous communications, to continue without interruption while the CPU idles, waiting for something to invoke an interrupt routine. Enabling the automatic return to full-speed CPU operation on interrupts is enabled by setting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation. For example, suppose the device is operating at 20 MIPS and the CAN module has been configured for 500 kbps based on this device operating speed. If the device is now placed in Doze mode with a clock frequency ratio of 1:4, the CAN module continues to communicate at the required bit rate of 500 kbps, but the CPU now starts executing instructions at a frequency of 5 MIPS. 9.2.3 INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS Any interrupt that coincides with the execution of a PWRSAV instruction is held off until entry into Sleep or Idle mode has completed. The device then wakes up from Sleep or Idle mode. 9.4 Peripheral Module Disable 9.3 Doze Mode Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. There may be circumstances, however, where this is not practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. Reducing system clock speed may introduce communication errors, while using a power-saving mode may stop communications completely. Doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. In this mode, the system clock continues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed, while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled via the appropriate PMD control bit, the peripheral is in a minimum power consumption state. The control and status registers associated with the peripheral are also disabled, so writes to those registers will have no effect and read values will be invalid. A peripheral module is only enabled if both the associated bit in the PMD register is cleared and the peripheral is supported by the specific dsPIC(R) DSC variant. If the peripheral is present in the device, it is enabled in the PMD register by default. Note: If a PMD bit is set, the corresponding module is disabled after a delay of 1 instruction cycle. Similarly, if a PMD bit is cleared, the corresponding module is enabled after a delay of 1 instruction cycle (assuming the module control registers are already configured to enable module operation). DS70165E-page 158 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 10.0 Note: I/O PORTS This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). When a peripheral is enabled and actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port. All port pins have three registers directly associated with their operation as digital I/O. The data direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a `1', then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx), read the latch. Writes to the latch, write the latch. Reads from the port (PORTx), read the port pins, while writes to the port pins, write the latch. Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pins will read as zeros. When a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competing source of outputs. An example is the INT4 pin. Note: The voltage on a digital input pin can be between -0.3V to 5.6V. All of the device pins (except VDD, VSS, MCLR and OSC1/CLKIN) are shared between the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt Trigger inputs for improved noise immunity. 10.1 Parallel I/O (PIO) Ports A parallel I/O port that shares a pin with a peripheral is, in general, subservient to the peripheral. The peripheral's output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pin. The logic also prevents "loop through", in which a port's digital output can drive the input of a peripheral that shares the same pin. Figure 10-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. FIGURE 10-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Peripheral Input Data Peripheral Module Enable Output Multiplexers I/O Peripheral Output Enable Peripheral Output Data 1 0 1 0 Output Enable PIO Module Read TRIS Output Data Data Bus WR TRIS D CK Q I/O Pin TRIS Latch D WR LAT + WR PORT CK Data Latch Q Read LAT Input Data Read Port (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 159 dsPIC33F 10.2 Open-Drain Configuration 10.4 I/O Port Write/Read Timing In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g., 5V) on any desired digital only pins by using external pull-up resistors. (The open-drain I/O feature is not supported on pins which have analog functionality multiplexed on the pin.) The maximum open-drain voltage allowed is the same as the maximum VIH specification. The open-drain output feature is supported for both port pin and peripheral configurations. One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP. 10.5 Input Change Notification The input change notification function of the I/O ports allows the dsPIC33F devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature is capable of detecting input change-of-states even in Sleep mode, when the clocks are disabled. Depending on the device pin count, there are up to 24 external signals (CN0 through CN23) that can be selected (enabled) for generating an interrupt request on a change-of-state. There are four control registers associated with the CN module. The CNEN1 and CNEN2 registers contain the CN interrupt enable (CNxIE) control bits for each of the CN input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. Each CN pin also has a weak pull-up connected to it. The pull-ups act as a current source that is connected to the pin and eliminate the need for external resistors when push button or keypad devices are connected. The pull-ups are enabled separately using the CNPU1 and CNPU2 registers, which contain the weak pull-up enable (CNxPUE) bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. 10.3 Configuring Analog Port Pins The use of the ADxPCFGH, ADxPCFGL and TRIS registers control the operation of the ADC port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) is converted. Clearing any bit in the ADxPCFGH or ADxPCFGL register configures the corresponding bit to be an analog pin. This is also the Reset state of any I/O pin that has an analog (ANx) function associated with it. Note: In devices with two ADC modules, if the corresponding PCFG bit in either AD1PCFGH(L) and AD2PCFGH(L) is cleared, the pin is configured as an analog input. When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will not convert an analog input. Analog levels on any pin that is defined as a digital input (including the ANx pins) can cause the input buffer to consume current that exceeds the device specifications. Note: The voltage on an analog input pin can be between -0.3V to (VDD + 0.3 V). EXAMPLE 10-1: MOV MOV NOP btss 0xFF00, W0 W0, TRISBB PORTB, #13 PORT WRITE/READ EXAMPLE ; ; ; ; Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs Delay 1 cycle Next Instruction DS70165E-page 160 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 11.0 Note: TIMER1 This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). Figure 11-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. 2. 3. 4. 5. 6. Set the TON bit (= 1) in the T1CON register. Select the timer prescaler ratio using the TCKPS<1:0> bits in the T1CON register. Set the Clock and Gating modes using the TCS and TGATE bits in the T1CON register. Set or clear the TSYNC bit in T1CON to select synchronous or asynchronous operation. Load the timer period value into the PR1 register. If interrupts are required, set the interrupt enable bit, T1IE. Use the priority bits, T1IP<2:0>, to set the interrupt priority. The Timer1 module is a 16-bit timer, which can serve as the time counter for the real-time clock, or operate as a free-running interval timer/counter. Timer1 can operate in three modes: * 16-bit Timer * 16-bit Synchronous Counter * 16-bit Asynchronous Counter Timer1 also supports these features: * Timer gate operation * Selectable prescaler settings * Timer operation during CPU Idle and Sleep modes * Interrupt on 16-bit Period register match or falling edge of external gate signal FIGURE 11-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM TCKPS<1:0> SOSCO/ T1CK SOSCEN SOSCI Gate Sync TCY TON 1x 2 Prescaler 1, 8, 64, 256 01 00 TGATE TCS TGATE 1 Set T1IF 0 Reset Q Q D CK 0 TMR1 1 Comparator TSYNC Sync Equal PR1 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 161 dsPIC33F REGISTER 11-1: R/W-0 TON bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE R/W-0 R/W-0 U-0 -- R/W-0 TSYNC R/W-0 TCS U-0 -- bit 0 T1CON: TIMER1 CONTROL REGISTER U-0 -- R/W-0 TSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 TCKPS<1:0> TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' TGATE: Timer1 Gated Time Accumulation Enable bit When T1CS = 1: This bit is ignored. When T1CS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS<1:0> Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 Unimplemented: Read as `0' TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronize external clock input 0 = Do not synchronize external clock input When TCS = 0: This bit is ignored. TCS: Timer1 Clock Source Select bit 1 = External clock from pin T1CK (on the rising edge) 0 = Internal clock (FCY) Unimplemented: Read as `0' bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3 bit 2 bit 1 bit 0 DS70165E-page 162 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 12.0 Note: TIMER2/3, TIMER4/5, TIMER6/7 AND TIMER8/9 This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). To configure Timer2/3, Timer4/5, Timer6/7 or Timer8/9 for 32-bit operation: 1. 2. 3. 4. Set the corresponding T32 control bit. Select the prescaler ratio for Timer2, Timer4, Timer6 or Timer8 using the TCKPS<1:0> bits. Set the Clock and Gating modes using the corresponding TCS and TGATE bits. Load the timer period value. PR3, PR5, PR7 or PR9 contains the most significant word of the value, while PR2, PR4, PR6 or PR8 contains the least significant word. If interrupts are required, set the interrupt enable bit, T3IE, T5IE, T7IE or T9IE. Use the priority bits, T3IP<2:0>, T5IP<2:0>, T7IP<2:0> or T9IP<2:0>, to set the interrupt priority. While Timer2, Timer4, Timer6 or Timer8 control the timer, the interrupt appears as a Timer3, Timer5, Timer7 or Timer9 interrupt. Set the corresponding TON bit. The Timer2/3, Timer4/5, Timer6/7 and Timer8/9 modules are 32-bit timers, which can also be configured as four independent 16-bit timers with selectable operating modes. As a 32-bit timer, Timer2/3, Timer4/5, Timer6/7 and Timer8/9 operate in three modes: * Two Independent 16-bit Timers (e.g., Timer2 and Timer3) with all 16-bit operating modes (except Asynchronous Counter mode) * Single 32-bit Timer * Single 32-bit Synchronous Counter They also support these features: Timer Gate Operation Selectable Prescaler Settings Timer Operation during Idle and Sleep modes Interrupt on a 32-bit Period Register Match Time Base for Input Capture and Output Compare Modules (Timer2 and Timer3 only) * ADC1 Event Trigger (Timer2/3 only) * ADC2 Event Trigger (Timer4/5 only) Individually, all eight of the 16-bit timers can function as synchronous timers or counters. They also offer the features listed above, except for the event trigger; this is implemented only with Timer2/3. The operating modes and enabled features are determined by setting the appropriate bit(s) in the T2CON, T3CON, T4CON, T5CON, T6CON, T7CON, T8CON and T9CON registers. T2CON, T4CON, T6CON and T8CON are shown in generic form in Register 12-1. T3CON, T5CON, T7CON and T9CON are shown in Register 12-2. For 32-bit timer/counter operation, Timer2, Timer4, Timer6 or Timer8 is the least significant word; Timer3, Timer5, Timer7 or Timer9 is the most significant word of the 32-bit timers. Note: For 32-bit operation, T3CON, T5CON, T7CON and T9CON control bits are ignored. Only T2CON, T4CON, T6CON and T8CON control bits are used for setup and control. Timer2, Timer4, Timer6 and Timer8 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3, Timer5, Ttimer7 and Timer9 interrupt flags. * * * * * 5. 6. The timer value at any point is stored in the register pair, TMR3:TMR2, TMR5:TMR4, TMR7:TMR6 or TMR9:TMR8. TMR3, TMR5, TMR7 or TMR9 always contains the most significant word of the count, while TMR2, TMR4, TMR6 or TMR8 contains the least significant word. To configure any of the timers for individual 16-bit operation: 1. 2. 3. 4. 5. Clear the T32 bit corresponding to that timer. Select the timer prescaler ratio using the TCKPS<1:0> bits. Set the Clock and Gating modes using the TCS and TGATE bits. Load the timer period value into the PRx register. If interrupts are required, set the interrupt enable bit, TxIE. Use the priority bits, TxIP<2:0>, to set the interrupt priority. Set the TON bit. 6. A block diagram for a 32-bit timer pair (Timer4/5) example is shown in Figure 12-1 and a timer (Timer4) operating in 16-bit mode example is shown in Figure 12-2. Note: Only Timer2 and Timer3 can trigger a DMA data transfer. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 163 dsPIC33F FIGURE 12-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM(1) TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 T2CK Gate Sync TCY TGATE 1x TON 01 00 TGATE TCS 1 Set T3IF 0 PR3 ADC Event Trigger(2) Q Q D CK PR2 Equal MSb Reset 16 Comparator LSb TMR3 TMR2 Sync Read TMR2 Write TMR2 16 16 TMR3HLD 16 Data Bus<15:0> Note 1: 2: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. The ADC event trigger is available only on Timer2/3. DS70165E-page 164 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 T2CK Gate Sync TON 1x 01 00 TCY TCS TGATE TGATE 1 Set T2IF 0 Reset TMR2 Q Q D CK Sync Comparator Equal PR2 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 165 dsPIC33F REGISTER 12-1: R/W-0 TON bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE R/W-0 R/W-0 R/W-0 T32 (1) TxCON (T2CON, T4CON, T6CON OR T8CON) CONTROL REGISTER U-0 -- R/W-0 TSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- R/W-0 TCS U-0 -- bit 0 TCKPS<1:0> TON: Timerx On bit When T32 = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-bit Timerx/y When T32 = 0: 1 = Starts 16-bit Timerx 0 = Stops 16-bit Timerx Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 T32: 32-bit Timer Mode Select bit(1) 1 = Timerx and Timery form a single 32-bit timer 0 = Timerx and Timery act as two 16-bit timers Unimplemented: Read as `0' TCS: Timerx Clock Source Select bit 1 = External clock from pin TxCK (on the rising edge) 0 = Internal clock (FCY) Unimplemented: Read as `0' In 32-bit mode, T3CON control bits do not affect 32-bit timer operation. bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3 bit 2 bit 1 bit 0 Note 1: DS70165E-page 166 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 12-2: R/W-0 TON bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE (1) (1) TyCON (T3CON, T5CON, T7CON OR T9CON) CONTROL REGISTER U-0 -- R/W-0 TSIDL(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 R/W-0 (1) U-0 -- U-0 -- R/W-0 TCS (1) U-0 -- bit 0 TCKPS<1:0> TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit(1) 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' TGATE: Timery Gated Time Accumulation Enable bit(1) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS<1:0>: Timer3 Input Clock Prescale Select bits(1) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 Unimplemented: Read as `0' TCS: Timery Clock Source Select bit(1) 1 = External clock from pin TyCK (on the rising edge) 0 = Internal clock (FCY) Unimplemented: Read as `0' When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON. bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3-2 bit 1 bit 0 Note 1: (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 167 dsPIC33F NOTES: DS70165E-page 168 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 13.0 Note: INPUT CAPTURE This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). Each input capture channel can select between one of two 16-bit timers (Timer2 or Timer3) for the time base. The selected timer can use either an internal or external clock. Other operational features include: * Device wake-up from capture pin during CPU Sleep and Idle modes * Interrupt on input capture event * 4-word FIFO buffer for capture values - Interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled * Input capture can also be used to provide additional sources of external interrupts Note: Only IC1 and IC2 can trigger a DMA data transfer. If DMA data transfers are required, the FIFO buffer size must be set to 1 (ICI<1:0> = 00). The input capture module is useful in applications requiring frequency (period) and pulse measurement. The dsPIC33F devices support up to eight input capture channels. The input capture module captures the 16-bit value of the selected Time Base register when an event occurs at the ICx pin. The events that cause a capture event are listed below in three categories: 1. Simple Capture Event modes -Capture timer value on every falling edge of input at ICx pin -Capture timer value on every rising edge of input at ICx pin Capture timer value on every edge (rising and falling) Prescaler Capture Event modes -Capture timer value on every 4th rising edge of input at ICx pin -Capture timer value on every 16th rising edge of input at ICx pin 2. 3. FIGURE 13-1: INPUT CAPTURE BLOCK DIAGRAM From 16-bit Timers TMRy TMRz 16 16 1 Prescaler Counter (1, 4, 16) ICx Pin 3 Edge Detection Logic and Clock Synchronizer ICM<2:0> (ICxCON<2:0>) Mode Select ICOV, ICBNE (ICxCON<4:3>) FIFO R/W Logic 0 ICTMR (ICxCON<7>) ICxBUF ICxI<1:0> ICxCON Interrupt Logic System Bus Set Flag ICxIF (in IFSn Register) Note: An `x' in a signal, register or bit name denotes the number of the capture channel. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 169 FIFO dsPIC33F 13.1 Input Capture Registers ICxCON: INPUT CAPTURE x CONTROL REGISTER U-0 -- R/W-0 ICSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 R/W-0 R-0, HC ICOV R-0, HC ICBNE R/W-0 R/W-0 ICM<2:0> bit 0 R/W-0 REGISTER 13-1: U-0 -- bit 15 R/W-0 ICTMR bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 (1) ICI<1:0> W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' ICSIDL: Input Capture Module Stop in Idle Control bit 1 = Input capture module will halt in CPU Idle mode 0 = Input capture module will continue to operate in CPU Idle mode Unimplemented: Read as `0' ICTMR: Input Capture Timer Select bits(1) 1 = TMR2 contents are captured on capture event 0 = TMR3 contents are captured on capture event ICI<1:0>: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event ICOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred ICBNE: Input Capture Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty ICM<2:0>: Input Capture Mode Select bits 111 =Input capture functions as interrupt pin only when device is in Sleep or Idle mode (Rising edge detect only, all other control bits are not applicable.) 110 =Unused (module disabled) 101 =Capture mode, every 16th rising edge 100 =Capture mode, every 4th rising edge 011 =Capture mode, every rising edge 010 =Capture mode, every falling edge 001 =Capture mode, every edge (rising and falling) (ICI<1:0> bits do not control interrupt generation for this mode.) 000 =Input capture module turned off Timer selections may vary. Refer to the device data sheet for details. bit 12-8 bit 7 bit 6-5 bit 4 bit 3 bit 2-0 Note 1: DS70165E-page 170 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 14.0 Note: OUTPUT COMPARE This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). The output compare module does not have to be disabled after the falling edge of the output pulse. Another pulse can be initiated by rewriting the value of the OCxCON register. 14.2 Setup for Continuous Output Pulse Generation 14.1 Setup for Single Output Pulse Generation When the OCM control bits (OCxCON<2:0>) are set to `100', the selected output compare channel initializes the OCx pin to the low state and generates a single output pulse. To generate a single output pulse, the following steps are required (these steps assume timer source is initially turned off but this is not a requirement for the module operation): 1. Determine the instruction clock cycle time. Take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. 2. Calculate time to the rising edge of the output pulse relative to the TMRy start value (0000h). 3. Calculate the time to the falling edge of the pulse based on the desired pulse width and the time to the rising edge of the pulse. 4. Write the values computed in steps 2 and 3 above into the Output Compare register, OCxR, and the Output Compare Secondary register, OCxRS, respectively. 5. Set Timer Period register, PRy, to value equal to or greater than value in OCxRS, the Output Compare Secondary register. 6. Set the OCM bits to `100' and the OCTSEL (OCxCON<3>) bit to the desired timer source. The OCx pin state will now be driven low. 7. Set the TON (TyCON<15>) bit to `1', which enables the compare time base to count. 8. Upon the first match between TMRy and OCxR, the OCx pin will be driven high. 9. When the incrementing timer, TMRy, matches the Output Compare Secondary register, OCxRS, the second and trailing edge (high-tolow) of the pulse is driven onto the OCx pin. No additional pulses are driven onto the OCx pin and it remains at low. As a result of the second compare match event, the OCxIF interrupt flag bit is set, which will result in an interrupt if it is enabled, by setting the OCxIE bit. For further information on peripheral interrupts, refer to Section 6.0 "Interrupt Controller". 10. To initiate another single pulse output, change the Timer and Compare register settings, if needed, and then issue a write to set the OCM bits to `100'. Disabling and re-enabling of the timer, and clearing the TMRy register, are not required but may be advantageous for defining a pulse from a known event time boundary. (c) 2007 Microchip Technology Inc. When the OCM control bits (OCxCON<2:0>) are set to `101', the selected output compare channel initializes the OCx pin to the low state and generates output pulses on each and every compare match event. For the user to configure the module for the generation of a continuous stream of output pulses, the following steps are required (these steps assume timer source is initially turned off but this is not a requirement for the module operation): Determine the instruction clock cycle time. Take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. 2. Calculate time to the rising edge of the output pulse relative to the TMRy start value (0000h). 3. Calculate the time to the falling edge of the pulse, based on the desired pulse width and the time to the rising edge of the pulse. 4. Write the values computed in step 2 and 3 above into the Output Compare register, OCxR, and the Output Compare Secondary register, OCxRS, respectively. 5. Set Timer Period register, PRy, to a value equal to or greater than value in OCxRS, the Output Compare Secondary register. 6. Set the OCM bits to `101' and the OCTSEL bit to the desired timer source. The OCx pin state will now be driven low. 7. Enable the compare time base by setting the TON (TyCON<15>) bit to `1'. 8. Upon the first match between TMRy and OCxR, the OCx pin will be driven high. 9. When the compare time base, TMRy, matches the Output Compare Secondary register, OCxRS, the second and trailing edge (high-to-low) of the pulse is driven onto the OCx pin. 10. As a result of the second compare match event, the OCxIF interrupt flag bit is set. 11. When the compare time base and the value in its respective Timer Period register match, the TMRy register resets to 0x0000 and resumes counting. 12. Steps 8 through 11 are repeated and a continuous stream of pulses is generated, indefinitely. The OCxIF flag is set on each OCxRS-TMRy compare match event. 1. Preliminary DS70165E-page 171 dsPIC33F 14.3 Pulse-Width Modulation Mode EQUATION 14-1: The following steps should be taken when configuring the output compare module for PWM operation: 1. 2. 3. 4. Set the PWM period by writing to the selected Timer Period register (PRy). Set the PWM duty cycle by writing to the OCxRS register. Write the OxCR register with the initial duty cycle. Enable interrupts, if required, for the timer and output compare modules. The output compare interrupt is required for PWM Fault pin utilization. Configure the output compare module for one of two PWM operation modes by writing to the Output Compare Mode bits, OCM<2:0> (OCxCON<2:0>). Set the TMRy prescale value and enable the time base by setting TON = 1 (TxCON<15>). Note: The OCxR register should be initialized before the output compare module is first enabled. The OCxR register becomes a read-only duty cycle register when the module is operated in the PWM modes. The value held in OCxR will become the PWM duty cycle for the first PWM period. The contents of the Output Compare Secondary register, OCxRS, will not be transferred into OCxR until a time base period match occurs. CALCULATING THE PWM PERIOD PWM Period = [(PRy) + 1] * TCY * (Timer Prescale Value) where: PWM Frequency = 1/[PWM Period] Note: A PRy value of N will produce a PWM period of N + 1 time base count cycles. For example, a value of 7 written into the PRy register will yield a period consisting of eight time base cycles. 5. 14.3.2 PWM DUTY CYCLE 6. The PWM duty cycle is specified by writing to the OCxRS register. The OCxRS register can be written to at any time, but the duty cycle value is not latched into OCxR until a match between PRy and TMRy occurs (i.e., the period is complete). This provides a double buffer for the PWM duty cycle and is essential for glitchless PWM operation. In the PWM mode, OCxR is a read-only register. Some important boundary parameters of the PWM duty cycle include: * If the Output Compare register, OCxR, is loaded with 0000h, the OCx pin will remain low (0% duty cycle). * If OCxR is greater than PRy (Timer Period register), the pin will remain high (100% duty cycle). * If OCxR is equal to PRy, the OCx pin will be low for one time base count value and high for all other count values. See Example 14-1 for PWM mode timing details. Table 14-1 shows example PWM frequencies and resolutions for a device operating at 10 MIPS. 14.3.1 PWM PERIOD The PWM period is specified by writing to PRy, the Timer Period register. The PWM period can be calculated using Equation 14-1: EQUATION 14-2: CALCULATION FOR MAXIMUM PWM RESOLUTION log10 Maximum PWM Resolution (bits) = FCY ( FPWM ) log10(2) bits EXAMPLE 14-1: 1. PWM PERIOD AND DUTY CYCLE CALCULATIONS 2. Find the Timer Period register value for a desired PWM frequency that is 52.08 kHz, where FCY = 16 MHz and a Timer2 prescaler setting of 1:1. TCY = 62.5 ns PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 s PWM Period = (PR2 + 1) * TCY * (Timer2 Prescale Value) 19.2 s = (PR2 + 1) * 62.5 ns * 1 PR2 = 306 Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate: PWM Resolution = log10 (FCY/FPWM)/log102) bits = (log10 (16 MHz/52.08 kHz)/log102) bits = 8.3 bits DS70165E-page 172 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F TABLE 14-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz) 7.6 Hz 8 FFFFh 16 61 Hz 1 FFFFh 16 122 Hz 1 7FFFh 15 977 Hz 1 0FFFh 12 3.9 kHz 1 03FFh 10 31.3 kHz 1 007Fh 7 125 kHz 1 001Fh 5 PWM Frequency Timer Prescaler Ratio Period Register Value Resolution (bits) TABLE 14-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz) 30.5 Hz 8 FFFFh 16 244 Hz 1 FFFFh 16 488 Hz 1 7FFFh 15 3.9 kHz 1 0FFFh 12 15.6 kHz 1 03FFh 10 125 kHz 1 007Fh 7 500 kHz 1 001Fh 5 PWM Frequency Timer Prescaler Ratio Period Register Value Resolution (bits) TABLE 14-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MIPS (FCY = 40 MHz) 76 Hz 8 FFFFh 16 610 Hz 1 FFFFh 16 1.22 Hz 1 7FFFh 15 9.77 kHz 1 0FFFh 12 39 kHz 1 03FFh 10 313 kHz 1 007Fh 7 1.25 MHz 1 001Fh 5 PWM Frequency Timer Prescaler Ratio Period Register Value Resolution (bits) FIGURE 14-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OCxIF(1) OCxRS(1) OCxR(1) Output Logic 3 SQ R Output Enable OCx(1) Comparator 0 1 OCTSEL 0 1 OCM2:OCM0 Mode Select OCFA or OCFB(2) 16 16 TMR register inputs from time bases(3) Period match signals from time bases(3) Note 1:Where `x' is shown, reference is made to the registers associated with the respective output compare channels 1 through 8. 2: OCFA pin controls OC1-OC4 channels. OCFB pin controls OC5-OC8 channels. 3: Each output compare channel can use one of two selectable time bases. Refer to the device data sheet for the time bases associated with the module. Note: Only OC1 and OC2 can trigger a DMA data transfer. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 173 dsPIC33F 14.4 Output Compare Register OCxCON: OUTPUT COMPARE x CONTROL REGISTER U-0 -- R/W-0 OCSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- R-0 HC OCFLT R/W-0 OCTSEL(1) R/W-0 R/W-0 OCM<2:0> bit 0 HC = Cleared in Hardware W = Writable bit `1' = Bit is set HS = Set in Hardware U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 REGISTER 14-1: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 Unimplemented: Read as `0' OCSIDL: Stop Output Compare in Idle Mode Control bit 1 = Output Compare x will halt in CPU Idle mode 0 = Output Compare x will continue to operate in CPU Idle mode Unimplemented: Read as `0' OCFLT: PWM Fault Condition Status bit 1 = PWM Fault condition has occurred (cleared in HW only) 0 = No PWM Fault condition has occurred (This bit is only used when OCM<2:0> = 111.) OCTSEL: Output Compare Timer Select bit(1) 1 = Timer3 is the clock source for Compare x 0 = Timer2 is the clock source for Compare x OCM<2:0>: Output Compare Mode Select bits 111 = PWM mode on OCx, Fault pin enabled 110 = PWM mode on OCx, Fault pin disabled 101 = Initialize OCx pin low, generate continuous output pulses on OCx pin 100 = Initialize OCx pin low, generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled Refer to the device data sheet for specific time bases available to the output compare module. bit 12-5 bit 4 bit 3 bit 2-0 Note 1: DS70165E-page 174 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 15.0 Note: MOTOR CONTROL PWM MODULE This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). This module contains 4 duty cycle generators, numbered 1 through 4. The module has eight PWM output pins, numbered PWM1H/PWM1L through PWM4H/PWM4L. The eight I/O pins are grouped into high/low numbered pairs, denoted by the suffix H or L, respectively. For complementary loads, the low PWM pins are always the complement of the corresponding high I/O pin. The PWM module allows several modes of operation which are beneficial for specific power control applications. This module simplifies the task of generating multiple, synchronized Pulse-Width Modulated (PWM) outputs. In particular, the following power and motion control applications are supported by the PWM module: * * * * * * * * * * * * * * 3-Phase AC Induction Motor Switched Reluctance (SR) Motor Brushless DC (BLDC) Motor Uninterruptible Power Supply (UPS) 8 PWM I/O pins with 4 duty cycle generators Up to 16-bit resolution `On-the-fly' PWM frequency changes Edge and Center-Aligned Output modes Single Pulse Generation mode Interrupt support for asymmetrical updates in Center-Aligned mode Output override control for Electrically Commutative Motor (ECM) operation `Special Event' comparator for scheduling other peripheral events Fault pins to optionally drive each of the PWM output pins to a defined state Duty cycle updates are configurable to be immediate or synchronized to the PWM time base The PWM module has the following features: (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 175 dsPIC33F FIGURE 15-1: PWM MODULE BLOCK DIAGRAM PWMCON1 PWM Enable and Mode SFRs PWMCON2 DTCON1 Dead-Time Control SFRs DTCON2 FLTACON Fault Pin Control SFRs FLTBCON OVDCON PWM Manual Control SFR PWM Generator #4 PDC4 Buffer 16-bit Data Bus PDC4 Comparator Channel 4 Dead-Time Generator and Override Logic PWM4H PWM4L PTMR PWM Generator #3 Channel 3 Dead-Time Generator and Override Logic PWM3H Output Driver PWM3L Comparator PWM Generator #2 PTPER PWM Generator #1 PTPER Buffer Channel 2 Dead-Time Generator and Override Logic Block PWM2H PWM2L Channel 1 Dead-Time Generator and Override Logic PWM1H PWM1L PTCON FLTA FLTB Comparator SEVTDIR SEVTCMP PTDIR Special Event Postscaler Special Event Trigger PWM Time Base Note: Details of PWM Generator #1, #2 and #3 not shown for clarity. DS70165E-page 176 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 15.1 PWM Time Base 15.1.1 FREE-RUNNING MODE The PWM time base is provided by a 15-bit timer with a prescaler and postscaler. The time base is accessible via the PTMR SFR. PTMR<15> is a read-only status bit, PTDIR, that indicates the present count direction of the PWM time base. If PTDIR is cleared, PTMR is counting upwards. If PTDIR is set, PTMR is counting downwards. The PWM time base is configured via the PTCON SFR. The time base is enabled/disabled by setting/clearing the PTEN bit in the PTCON SFR. PTMR is not cleared when the PTEN bit is cleared in software. The PTPER SFR sets the counting period for PTMR. The user must write a 15-bit value to PTPER<14:0>. When the value in PTMR<14:0> matches the value in PTPER<14:0>, the time base will either reset to `0' or reverse the count direction on the next occurring clock cycle. The action taken depends on the operating mode of the time base. Note: If the PWM Period register is set to 0x0000, the timer will stop counting and the interrupt and Special Event Trigger will not be generated, even if the special event value is also 0x0000. The module will not update the PWM Period register if it is already at 0x0000; therefore, the user must disable the module in order to update the PWM Period register. In Free-Running mode, the PWM time base counts upwards until the value in the PWM Time Base Period register (PTPER) is matched. The PTMR register is reset on the following input clock edge, and the time base will continue to count upwards as long as the PTEN bit remains set. When the PWM time base is in the Free-Running mode (PTMOD<1:0> = 00), an interrupt event is generated each time a match with the PTPER register occurs and the PTMR register is reset to zero. The postscaler selection bits may be used in this mode of the timer to reduce the frequency of the interrupt events. 15.1.2 SINGLE-SHOT MODE In Single-Shot mode, the PWM time base begins counting upwards when the PTEN bit is set. When the value in the PTMR register matches the PTPER register, the PTMR register will be reset on the following input clock edge, and the PTEN bit will be cleared by the hardware to halt the time base. When the PWM time base is in the Single-Shot mode (PTMOD<1:0> = 01), an interrupt event is generated when a match with the PTPER register occurs. The PTMR register is reset to zero on the following input clock edge and the PTEN bit is cleared. The postscaler selection bits have no effect in this mode of the timer. The PWM time base can be configured for four different modes of operation: * * * * Free-Running mode Single-Shot mode Continuous Up/Down Count mode Continuous Up/Down Count mode with interrupts for double updates 15.1.3 CONTINUOUS UP/DOWN COUNT MODES These four modes are selected by the PTMOD<1:0> bits in the PTCON SFR. The Up/Down Count modes support center-aligned PWM generation. The SingleShot mode allows the PWM module to support pulse control of certain Electronically Commutative Motors (ECMs). The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. In the Continuous Up/Down Count modes, the PWM time base counts upwards until the value in the PTPER register is matched. The timer will begin counting downwards on the following input clock edge. The PTDIR bit in the PTMR SFR is read-only and indicates the counting direction. The PTDIR bit is set when the timer counts downwards. In the Up/Down Count mode (PTMOD<1:0> = 10), an interrupt event is generated each time the value of the PTMR register becomes zero and the PWM time base begins to count upwards. The postscaler selection bits may be used in this mode of the timer to reduce the frequency of the interrupt events. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 177 dsPIC33F 15.1.4 DOUBLE UPDATE MODE In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR register is equal to zero, as well as each time a period match occurs. The postscaler selection bits have no effect in this mode of the timer. The Double Update mode provides two additional functions to the user. First, the control loop bandwidth is doubled because the PWM duty cycles can be updated, twice per period. Second, asymmetrical center-aligned PWM waveforms can be generated, which are useful for minimizing output waveform distortion in certain motor control applications. Note: Programming a value of 0x0001 in the PWM Period register could generate a continuous interrupt pulse and hence, must be avoided. The PWM period Equation 15-1: can be determined using EQUATION 15-1: TPWM = PWM PERIOD TCY * (PTPER + 1) (PTMR Prescale Value) If the PWM time base is configured for one of the Up/ Down Count modes, the PWM period will be twice the value provided by Equation 15-1. The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined using Equation 15-2: EQUATION 15-2: PWM RESOLUTION log (2 * TPWM/TCY) log (2) 15.1.5 PWM TIME BASE PRESCALER Resolution = The input clock to PTMR (FOSC/4) has prescaler options of 1:1, 1:4, 1:16 or 1:64, selected by control bits, PTCKPS<1:0>, in the PTCON SFR. The prescaler counter is cleared when any of the following occurs: * a write to the PTMR register * a write to the PTCON register * any device Reset The PTMR register is not cleared when PTCON is written. 15.3 Edge-Aligned PWM 15.1.6 PWM TIME BASE POSTSCALER Edge-aligned PWM signals are produced by the module when the PWM time base is in Free-Running or SingleShot mode. For edge-aligned PWM outputs, the output has a period specified by the value in PTPER and a duty cycle specified by the appropriate Duty Cycle register (see Figure 15-2). The PWM output is driven active at the beginning of the period (PTMR = 0) and is driven inactive when the value in the Duty Cycle register matches PTMR. If the value in a particular Duty Cycle register is zero, then the output on the corresponding PWM pin will be inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is greater than the value held in the PTPER register. The match output of PTMR can optionally be postscaled through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling). The postscaler counter is cleared when any of the following occurs: * a write to the PTMR register * a write to the PTCON register * any device Reset The PTMR register is not cleared when PTCON is written. FIGURE 15-2: EDGE-ALIGNED PWM New Duty Cycle Latched 15.2 PWM Period PTPER PTMR Value PTPER is a 15-bit register and is used to set the counting period for the PWM time base. PTPER is a doublebuffered register. The PTPER buffer contents are loaded into the PTPER register at the following instants: * Free-Running and Single-Shot modes: When the PTMR register is reset to zero after a match with the PTPER register. * Up/Down Count modes: When the PTMR register is zero. The value held in the PTPER buffer is automatically loaded into the PTPER register when the PWM time base is disabled (PTEN = 0). 0 Duty Cycle Period DS70165E-page 178 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 15.4 Center-Aligned PWM 15.5.1 DUTY CYCLE REGISTER BUFFERS Center-aligned PWM signals are produced by the module when the PWM time base is configured in an Up/Down Count mode (see Figure 15-3). The PWM compare output is driven to the active state when the value of the Duty Cycle register matches the value of PTMR and the PWM time base is counting downwards (PTDIR = 1). The PWM compare output is driven to the inactive state when the PWM time base is counting upwards (PTDIR = 0) and the value in the PTMR register matches the duty cycle value. If the value in a particular Duty Cycle register is zero, then the output on the corresponding PWM pin will be inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is equal to the value held in the PTPER register. The four PWM Duty Cycle registers are doublebuffered to allow glitchless updates of the PWM outputs. For each duty cycle, there is a Duty Cycle register that is accessible by the user and a second Duty Cycle register that holds the actual compare value used in the present PWM period. For edge-aligned PWM output, a new duty cycle value will be updated whenever a match with the PTPER register occurs and PTMR is reset. The contents of the duty cycle buffers are automatically loaded into the Duty Cycle registers when the PWM time base is disabled (PTEN = 0) and the UDIS bit is cleared in PWMCON2. When the PWM time base is in the Up/Down Count mode, new duty cycle values are updated when the value of the PTMR register is zero, and the PWM time base begins to count upwards. The contents of the duty cycle buffers are automatically loaded into the Duty Cycle registers when the PWM time base is disabled (PTEN = 0). When the PWM time base is in the Up/Down Count mode with double updates, new duty cycle values are updated when the value of the PTMR register is zero, and when the value of the PTMR register matches the value in the PTPER register. The contents of the duty cycle buffers are automatically loaded into the Duty Cycle registers when the PWM time base is disabled (PTEN = 0). FIGURE 15-3: CENTER-ALIGNED PWM Period/2 PTPER Duty Cycle PTMR Value 0 15.5.2 Period DUTY CYCLE IMMEDIATE UPDATES 15.5 PWM Duty Cycle Comparison Units There are four 16-bit Special Function Registers (PDC1, PDC2, PDC3 and PDC4) used to specify duty cycle values for the PWM module. The value in each Duty Cycle register determines the amount of time that the PWM output is in the active state. The Duty Cycle registers are 16 bits wide. The LSb of a Duty Cycle register determines whether the PWM edge occurs in the beginning. Thus, the PWM resolution is effectively doubled. When the Immediate Update Enable bit is set (IUE = 1), any write to the Duty Cycle registers will update the new duty cycle value immediately. This feature gives the option to the user to allow immediate updates of the active PWM Duty Cycle registers instead of waiting for the end of the current time base period. System stability is improved in closed-loop servo applications by reducing the delay between system observation and the issuance of system corrective commands when immediate updates are enabled (IUE = 1). If the PWM output is active at the time the new duty cycle is written and the new duty cycle is less than the current time base value, the PWM pulse width will be shortened. If the PWM output is active at the time the new duty cycle is written and the new duty cycle is greater than the current time base value, the PWM pulse width will be lengthened. If the PWM output is inactive at the time the new duty cycle is written and the new duty cycle is greater than the current time base value, the PWM output will become active immediately and will remain active for the new written duty cycle value. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 179 dsPIC33F 15.6 Complementary PWM Operation In the Complementary mode of operation, each pair of PWM outputs is obtained by a complementary PWM signal. A dead time may be optionally inserted during device switching, when both outputs are inactive for a short period (refer to Section 15.7 "Dead-Time Generators"). In Complementary mode, the duty cycle comparison units are assigned to the PWM outputs as follows: * * * * PDC1 register controls PWM1H/PWM1L outputs PDC2 register controls PWM2H/PWM2L outputs PDC3 register controls PWM3H/PWM3L outputs PDC4 register controls PWM4H/PWM4L outputs The PWM module allows two different dead times to be programmed. These two dead times may be used in one of two methods, described below, to increase user flexibility: * The PWM output signals can be optimized for different turn-off times in the high side and low side transistors in a complementary pair of transistors. The first dead time is inserted between the turn-off event of the lower transistor of the complementary pair and the turn-on event of the upper transistor. The second dead time is inserted between the turn-off event of the upper transistor and the turn-on event of the lower transistor. * The two dead times can be assigned to individual PWM I/O pin pairs. This operating mode allows the PWM module to drive different transistor/load combinations with each complementary PWM I/O pin pair. The Complementary mode is selected for each PWM I/O pin pair by clearing the appropriate PMODx bit in the PWMCON1 SFR. The PWM I/O pins are set to Complementary mode by default upon a device Reset. 15.7.1 DEAD-TIME GENERATORS 15.7 Dead-Time Generators Dead-time generation may be provided when any of the PWM I/O pin pairs are operating in the Complementary Output mode. The PWM outputs use push-pull drive circuits. Due to the inability of the power output devices to switch instantaneously, some amount of time must be provided between the turn-off event of one PWM output in a complementary pair and the turn-on event of the other transistor. Each complementary output pair for the PWM module has a 6-bit down counter that is used to produce the dead-time insertion. As shown in Figure 15-4, each dead-time unit has a rising and falling edge detector connected to the duty cycle comparison output. FIGURE 15-4: DEAD-TIME TIMING DIAGRAM Duty Cycle Generator PWMxH PWMxL Time Selected by DTSxA bit (A or B) Time Selected by DTSxI bit (A or B) DS70165E-page 180 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 15.7.2 DEAD-TIME ASSIGNMENT 15.8 Independent PWM Output The DTCON2 SFR contains control bits that allow the dead times to be assigned to each of the complementary outputs. Table 15-1 summarizes the function of each dead-time selection control bit. TABLE 15-1: Bit DTS1A DTS1I DTS2A DTS2I DTS3A DTS3I DTS4A DTS4I DEAD-TIME SELECTION BITS Function An Independent PWM Output mode is required for driving certain types of loads. A particular PWM output pair is in the Independent Output mode when the corresponding PMODx bit in the PWMCON1 register is set. No dead-time control is implemented between adjacent PWM I/O pins when the module is operating in the Independent PWM Output mode and both I/O pins are allowed to be active simultaneously. In the Independent PWM Output mode, each duty cycle generator is connected to both of the PWM I/O pins in an output pair. By using the associated Duty Cycle register and the appropriate bits in the OVDCON register, the user may select the following signal output options for each PWM I/O pin operating in this mode: * I/O pin outputs PWM signal * I/O pin inactive * I/O pin active Selects PWM1L/PWM1H active edge dead time. Selects PWM1L/PWM1H inactive edge dead time. Selects PWM2L/PWM2H active edge dead time. Selects PWM2L/PWM2H inactive edge dead time. Selects PWM3L/PWM3H active edge dead time. Selects PWM3L/PWM3H inactive edge dead time. Selects PWM4L/PWM4H active edge dead time. Selects PWM4L/PWM4H inactive edge dead time. 15.9 Single Pulse PWM Operation 15.7.3 DEAD-TIME RANGES The amount of dead time provided by each dead-time unit is selected by specifying the input clock prescaler value and a 6-bit unsigned value. The amount of dead time provided by each unit may be set independently. Four input clock prescaler selections have been provided to allow a suitable range of dead times, based on the device operating frequency. The clock prescaler option may be selected independently for each of the two dead-time values. The dead-time clock prescaler values are selected using the DTAPS<1:0> and DTBPS<1:0> control bits in the DTCON1 SFR. One of four clock prescaler options (TCY, 2 TCY, 4 TCY or 8 TCY) may be selected for each of the dead-time values. After the prescaler values are selected, the dead time for each unit is adjusted by loading two 6-bit unsigned values into the DTCON1 SFR. The dead-time unit prescalers are cleared on the following events: * On a load of the down timer due to a duty cycle comparison edge event. * On a write to the DTCON1 or DTCON2 registers. * On any device Reset. Note: The user should not modify the DTCON1 or DTCON2 values while the PWM module is operating (PTEN = 1). Unexpected results may occur. The PWM module produces single pulse outputs when the PTCON control bits PTMOD<1:0> = 10. Only edgealigned outputs may be produced in the Single Pulse mode. In Single Pulse mode, the PWM I/O pin(s) are driven to the active state when the PTEN bit is set. When a match with a Duty Cycle register occurs, the PWM I/O pin is driven to the inactive state. When a match with the PTPER register occurs, the PTMR register is cleared, all active PWM I/O pins are driven to the inactive state, the PTEN bit is cleared and an interrupt is generated. 15.10 PWM Output Override The PWM output override bits allow the user to manually drive the PWM I/O pins to specified logic states, independent of the duty cycle comparison units. All control bits associated with the PWM output override function are contained in the OVDCON register. The upper half of the OVDCON register contains eight bits, POVDxH<4:1> and POVDxL<4:1>, that determine which PWM I/O pins will be overridden. The lower half of the OVDCON register contains eight bits, POUTxH<4:1> and POUTxL<4:1>, that determine the state of the PWM I/O pins when a particular output is overridden via the POVD bits. 15.10.1 COMPLEMENTARY OUTPUT MODE When a PWMxL pin is driven active via the OVDCON register, the output signal is forced to be the complement of the corresponding PWMxH pin in the pair. Dead-time insertion is still performed when PWM channels are overridden manually. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 181 dsPIC33F 15.10.2 OVERRIDE SYNCHRONIZATION 15.12.1 FAULT PIN ENABLE BITS If the OSYNC bit in the PWMCON2 register is set, all output overrides performed via the OVDCON register are synchronized to the PWM time base. Synchronous output overrides occur at the following times: * Edge-Aligned mode - when PTMR is zero * Center-Aligned modes - when PTMR is zero and the value of PTMR matches PTPER The FLTACON and FLTBCON SFRs each have four control bits that determine whether a particular pair of PWM I/O pins is to be controlled by the Fault input pin. To enable a specific PWM I/O pin pair for Fault overrides, the corresponding bit should be set in the FLTACON or FLTBCON register. If all enable bits are cleared in the FLTACON or FLTBCON register, then the corresponding Fault input pin has no effect on the PWM module and the pin may be used as a general purpose interrupt or I/O pin. Note: The Fault pin logic can operate independent of the PWM logic. If all the enable bits in the FLTACON/FLTBCON registers are cleared, then the Fault pin(s) could be used as general purpose interrupt pin(s). Each Fault pin has an interrupt vector, interrupt flag bit and interrupt priority bits associated with it. 15.11 PWM Output and Polarity Control There are three device Configuration bits associated with the PWM module that provide PWM output pin control: * HPOL Configuration bit * LPOL Configuration bit * PWMPIN Configuration bit These three bits in the FPOR Configuration register (see Section 23.0 "Special Features") work in conjunction with the eight PWM Enable bits (PENxH<4:1>, PENxL<4:1>) located in the PWMCON1 SFR. The Configuration bits and PWM Enable bits ensure that the PWM pins are in the correct states after a device Reset occurs. The PWMPIN configuration fuse allows the PWM module outputs to be optionally enabled on a device Reset. If PWMPIN = 0, the PWM outputs will be driven to their inactive states at Reset. If PWMPIN = 1 (default), the PWM outputs will be tri-stated. The HPOL bit specifies the polarity for the PWMxH outputs, whereas the LPOL bit specifies the polarity for the PWMxL outputs. 15.12.2 FAULT STATES The FLTACON and FLTBCON Special Function Registers have eight bits each that determine the state of each PWM I/O pin when it is overridden by a Fault input. When these bits are cleared, the PWM I/O pin is driven to the inactive state. If the bit is set, the PWM I/O pin will be driven to the active state. The active and inactive states are referenced to the polarity defined for each PWM I/O pin (HPOL and LPOL polarity control bits). A special case exists when a PWM module I/O pair is in the Complementary mode and both pins are programmed to be active on a Fault condition. The PWMxH pin always has priority in the Complementary mode so that both I/O pins cannot be driven active simultaneously. 15.11.1 OUTPUT PIN CONTROL The PENxH<4:1> and PENxL<4:1> control bits in the PWMCON1 SFR enable each high PWM output pin and each low PWM output pin, respectively. If a particular PWM output pin is not enabled, it is treated as a general purpose I/O pin. 15.12.3 FAULT PIN PRIORITY 15.12 PWM Fault Pins There are two Fault pins (FLTA and FLTB) associated with the PWM module. When asserted, these pins can optionally drive each of the PWM I/O pins to a defined state. If both Fault input pins have been assigned to control a particular PWM I/O pin, the Fault state programmed for the Fault A input pin will take priority over the Fault B input pin. DS70165E-page 182 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 15.12.4 FAULT INPUT MODES 15.14 PWM Special Event Trigger The PWM module has a Special Event Trigger that allows ADC conversions to be synchronized to the PWM time base. The ADC sampling and conversion time may be programmed to occur at any point within the PWM period. The Special Event Trigger allows the user to minimize the delay between the time when ADC conversion results are acquired and the time when the duty cycle value is updated. The PWM Special Event Trigger has an SFR named SEVTCMP, and five control bits to control its operation. The PTMR value for which a Special Event Trigger should occur is loaded into the SEVTCMP register. When the PWM time base is in an Up/Down Count mode, an additional control bit is required to specify the counting phase for the Special Event Trigger. The count phase is selected using the SEVTDIR control bit in the SEVTCMP SFR. If the SEVTDIR bit is cleared, the Special Event Trigger will occur on the upward counting cycle of the PWM time base. If the SEVTDIR bit is set, the Special Event Trigger will occur on the downward count cycle of the PWM time base. The SEVTDIR control bit has no effect unless the PWM time base is configured for an Up/Down Count mode. Each of the Fault input pins have two modes of operation: * Latched Mode: When the Fault pin is driven low, the PWM outputs will go to the states defined in the FLTACON/FLTBCON registers. The PWM outputs will remain in this state until the Fault pin is driven high and the corresponding interrupt flag has been cleared in software. When both of these actions have occurred, the PWM outputs will return to normal operation at the beginning of the next PWM cycle or half-cycle boundary. If the interrupt flag is cleared before the Fault condition ends, the PWM module will wait until the Fault pin is no longer asserted, to restore the outputs. * Cycle-by-Cycle Mode: When the Fault input pin is driven low, the PWM outputs remain in the defined Fault states for as long as the Fault pin is held low. After the Fault pin is driven high, the PWM outputs return to normal operation at the beginning of the following PWM cycle or half-cycle boundary. The operating mode for each Fault input pin is selected using the FLTAM and FLTBM control bits in the FLTACON and FLTBCON Special Function Registers. Each of the Fault pins can be controlled manually in software. 15.14.1 SPECIAL EVENT TRIGGER POSTSCALER 15.13 PWM Update Lockout For a complex PWM application, the user may need to write up to four Duty Cycle registers and the PWM Time Base Period register, PTPER, at a given time. In some applications, it is important that all buffer registers be written before the new duty cycle and period values are loaded for use by the module. The PWM update lockout feature is enabled by setting the UDIS control bit in the PWMCON2 SFR. The UDIS bit affects all Duty Cycle Buffer registers and the PWM Time Base Period register, PTPER. No duty cycle changes or period value changes will have effect while UDIS = 1. If the IUE bit is set, any change to the Duty Cycle registers will be immediately updated regardless of the UDIS bit state. The PWM Period register (PTPER) updates are not affected by the IUE control bit. The PWM Special Event Trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio. The postscaler is configured by writing the SEVOPS<3:0> control bits in the PWMCON2 SFR. The special event output postscaler is cleared on the following events: * Any write to the SEVTCMP register * Any device Reset 15.15 PWM Operation During CPU Sleep Mode The Fault A and Fault B input pins have the ability to wake the CPU from Sleep mode. The PWM module generates an interrupt if either of the Fault pins is driven low while in Sleep. 15.16 PWM Operation During CPU Idle Mode The PTCON SFR contains a PTSIDL control bit. This bit determines if the PWM module will continue to operate or stop when the device enters Idle mode. If PTSIDL = 0, the module will continue to operate. If PTSIDL = 1, the module will stop operation as long as the CPU remains in Idle mode. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 183 dsPIC33F REGISTER 15-1: R/W-0 PTEN bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTCON: PWM TIME BASE CONTROL REGISTER U-0 -- R/W-0 PTSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 bit 0 PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0> PTEN: PWM Time Base Timer Enable bit 1 = PWM time base is on 0 = PWM time base is off Unimplemented: Read as `0' PTSIDL: PWM Time Base Stop in Idle Mode bit 1 = PWM time base halts in CPU Idle mode 0 = PWM time base runs in CPU Idle mode Unimplemented: Read as `0' PTOPS<3:0>: PWM Time Base Output Postscale Select bits 1111 = 1:16 postscale * * 0001 = 1:2 postscale 0000 = 1:1 postscale PTCKPS<1:0>: PWM Time Base Input Clock Prescale Select bits 11 = PWM time base input clock period is 64 TCY (1:64 prescale) 10 = PWM time base input clock period is 16 TCY (1:16 prescale) 01 = PWM time base input clock period is 4 TCY (1:4 prescale) 00 = PWM time base input clock period is TCY (1:1 prescale) PTMOD<1:0>: PWM Time Base Mode Select bits 11 =PWM time base operates in a Continuous Up/Down Count mode with interrupts for double PWM updates 10 =PWM time base operates in a Continuous Up/Down Count mode 01 =PWM time base operates in Single Pulse mode 00 =PWM time base operates in a Free-Running mode bit 14 bit 13 bit 12-8 bit 7-4 bit 3-2 bit 1-0 DS70165E-page 184 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 15-2: R-0 PTDIR bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTMR: PWM TIMER COUNT VALUE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 PTMR<14:8> bit 8 R/W-0 bit 0 R/W-0 R/W-0 R/W-0 PTMR<7:0> PTDIR: PWM Time Base Count Direction Status bit (read-only) 1 = PWM time base is counting down 0 = PWM time base is counting up PTMR <14:0>: PWM Time Base Register Count Value bits bit 14-0 REGISTER 15-3: U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-0 PTPER: PWM TIME BASE PERIOD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 PTPER<14:8> bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 R/W-0 R/W-0 R/W-0 PTPER<7:0> W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' PTPER<14:0>: PWM Time Base Period Value bits (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 185 dsPIC33F REGISTER 15-4: R/W-0 SEVTDIR(1) bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP: SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP<14:8>(2) bit 8 R/W-0 bit 0 R/W-0 R/W-0 R/W-0 SEVTCMP<7:0>(2) SEVTDIR: Special Event Trigger Time Base Direction bit(1) 1 = A Special Event Trigger will occur when the PWM time base is counting downwards 0 = A Special Event Trigger will occur when the PWM time base is counting upwards SEVTCMP<14:0>: Special Event Compare Value bits(2) SEVTDIR is compared with PTDIR (PTMR<15>) to generate the Special Event Trigger. SEVTCMP<14:0> is compared with PTMR<14:0> to generate the Special Event Trigger. bit 14-0 Note 1: 2: DS70165E-page 186 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 15-5: U-0 -- bit 15 R/W-1 PEN4H bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown (1) PWMCON1: PWM CONTROL REGISTER 1 U-0 -- U-0 -- U-0 -- R/W-0 PMOD4 R/W-0 PMOD3 R/W-0 PMOD2 R/W-0 PMOD1 bit 8 R/W-1 R/W-1 PEN2H (1) R/W-1 PEN1H (1) R/W-1 PEN4L (1) R/W-1 PEN3L (1) R/W-1 PEN2L (1) R/W-1 PEN1L(1) bit 0 PEN3H (1) Unimplemented: Read as `0' PMOD<4:1>: PWM I/O Pair Mode bits 1 = PWM I/O pin pair is in the Independent PWM Output mode 0 = PWM I/O pin pair is in the Complementary Output mode PEN4H:PEN1H: PWMxH I/O Enable bits(1) 1 = PWMxH pin is enabled for PWM output 0 = PWMxH pin disabled, I/O pin becomes general purpose I/O PEN4L:PEN1L: PWMxL I/O Enable bits(1) 1 = PWMxL pin is enabled for PWM output 0 = PWMxL pin disabled, I/O pin becomes general purpose I/O Reset condition of the PENxH and PENxL bits depends on the value of the PWMPIN Configuration bit in the FPOR Configuration register. bit 7-4 bit 3-0 Note 1: (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 187 dsPIC33F REGISTER 15-6: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 IUE R/W-0 OSYNC PWMCON2: PWM CONTROL REGISTER 2 U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 UDIS bit 0 SEVOPS<3:0> Unimplemented: Read as `0' SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits 1111 = 1:16 postscale * * 0001 = 1:2 postscale 0000 = 1:1 postscale Unimplemented: Read as `0' IUE: Immediate Update Enable bit 1 = Updates to the active PDC registers are immediate 0 = Updates to the active PDC registers are synchronized to the PWM time base OSYNC: Output Override Synchronization bit 1 = Output overrides via the OVDCON register are synchronized to the PWM time base 0 = Output overrides via the OVDCON register occur on next TCY boundary UDIS: PWM Update Disable bit 1 = Updates from Duty Cycle and Period Buffer registers are disabled 0 = Updates from Duty Cycle and Period Buffer registers are enabled bit 7-3 bit 2 bit 1 bit 0 DS70165E-page 188 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 15-7: R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTBPS<1:0> DTCON1: DEAD-TIME CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 DTB<5:0> DTAPS<1:0> DTA<5:0> DTBPS<1:0>: Dead-Time Unit B Prescale Select bits 11 = Clock period for Dead-Time Unit B is 8 TCY 10 = Clock period for Dead-Time Unit B is 4 TCY 01 = Clock period for Dead-Time Unit B is 2 TCY 00 = Clock period for Dead-Time Unit B is TCY DTB<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit B bits DTAPS<1:0>: Dead-Time Unit A Prescale Select bits 11 = Clock period for Dead-Time Unit A is 8 TCY 10 = Clock period for Dead-Time Unit A is 4 TCY 01 = Clock period for Dead-Time Unit A is 2 TCY 00 = Clock period for Dead-Time Unit A is TCY DTA<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit A bits bit 13-8 bit 7-6 bit 5-0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 189 dsPIC33F REGISTER 15-8: U-0 -- bit 15 R/W-0 DTS4A bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 DTS4I R/W-0 DTS3A R/W-0 DTS3I R/W-0 DTS2A R/W-0 DTS2I R/W-0 DTS1A DTCON2: DEAD-TIME CONTROL REGISTER 2 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 DTS1I bit 0 Unimplemented: Read as `0' DTS4A: Dead-Time Select for PWM4 Signal Going Active bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A DTS4I: Dead-Time Select for PWM4 Signal Going Inactive bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A DTS3A: Dead-Time Select for PWM3 Signal Going Active bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A DTS3I: Dead-Time Select for PWM3 Signal Going Inactive bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A DTS2A: Dead-Time Select for PWM2 Signal Going Active bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A DTS2I: Dead-Time Select for PWM2 Signal Going Inactive bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A DTS1A: Dead-Time Select for PWM1 Signal Going Active bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A DTS1I: Dead-Time Select for PWM1 Signal Going Inactive bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS70165E-page 190 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 15-9: R/W-0 FAOV4H bit 15 R/W-0 FLTAM bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/W-0 FAEN4 R/W-0 FAEN3 R/W-0 FAEN2 FLTACON: FAULT A CONTROL REGISTER R/W-0 R/W-0 FAOV3H R/W-0 FAOV3L R/W-0 FAOV2H R/W-0 FAOV2L R/W-0 FAOV1H R/W-0 FAOV1L bit 8 R/W-0 FAEN1 bit 0 FAOV4L FAOVxH<4:1>:FAOVxL<4:1>: Fault Input A PWM Override Value bits 1 = The PWM output pin is driven active on an external Fault input event 0 = The PWM output pin is driven inactive on an external Fault input event FLTAM: Fault A Mode bit 1 = The Fault A input pin functions in the Cycle-by-Cycle mode 0 = The Fault A input pin latches all control pins to the programmed states in FLTACON<15:8> Unimplemented: Read as `0' FAEN4: Fault Input A Enable bit 1 = PWM4H/PWM4L pin pair is controlled by Fault Input A 0 = PWM4H/PWM4L pin pair is not controlled by Fault Input A FAEN3: Fault Input A Enable bit 1 = PWM3H/PWM3L pin pair is controlled by Fault Input A 0 = PWM3H/PWM3L pin pair is not controlled by Fault Input A FAEN2: Fault Input A Enable bit 1 = PWM2H/PWM2L pin pair is controlled by Fault Input A 0 = PWM2H/PWM2L pin pair is not controlled by Fault Input A FAEN1: Fault Input A Enable bit 1 = PWM1H/PWM1L pin pair is controlled by Fault Input A 0 = PWM1H/PWM1L pin pair is not controlled by Fault Input A bit 7 bit 6-4 bit 3 bit 2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 191 dsPIC33F REGISTER 15-10: FLTBCON: FAULT B CONTROL REGISTER R/W-0 FBOV4H bit 15 R/W-0 FLTBM bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/W-0 FBEN4(1) R/W-0 FBEN3(1) R/W-0 FBEN2(1) R/W-0 FBOV4L R/W-0 FBOV3H R/W-0 FBOV3L R/W-0 FBOV2H R/W-0 FBOV2L R/W-0 FBOV1H R/W-0 FBOV1L bit 8 R/W-0 FBEN1(1) bit 0 FBOVxH<4:1>:FBOVxL<4:1>: Fault Input B PWM Override Value bits 1 = The PWM output pin is driven active on an external Fault input event 0 = The PWM output pin is driven inactive on an external Fault input event FLTBM: Fault B Mode bit 1 = The Fault B input pin functions in the Cycle-by-Cycle mode 0 = The Fault B input pin latches all control pins to the programmed states in FLTBCON<15:8> Unimplemented: Read as `0' FBEN4: Fault Input B Enable bit(1) 1 = PWM4H/PWM4L pin pair is controlled by Fault Input B 0 = PWM4H/PWM4L pin pair is not controlled by Fault Input B FBEN3: Fault Input B Enable bit(1) 1 = PWM3H/PWM3L pin pair is controlled by Fault Input B 0 = PWM3H/PWM3L pin pair is not controlled by Fault Input B FBEN2: Fault Input B Enable bit(1) 1 = PWM2H/PWM2L pin pair is controlled by Fault Input B 0 = PWM2H/PWM2L pin pair is not controlled by Fault Input B FBEN1: Fault Input B Enable bit(1) 1 = PWM1H/PWM1L pin pair is controlled by Fault Input B 0 = PWM1H/PWM1L pin pair is not controlled by Fault Input B Fault A pin has priority over Fault B pin, if enabled. bit 7 bit 6-4 bit 3 bit 2 bit 1 bit 0 Note 1: DS70165E-page 192 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 15-11: OVDCON: OVERRIDE CONTROL REGISTER R/W-1 POVD4H bit 15 R/W-0 POUT4H bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 POUT4L R/W-0 POUT3H R/W-0 POUT3L R/W-0 POUT2H R/W-0 POUT2L R/W-0 POUT1H R/W-1 POVD4L R/W-1 POVD3H R/W-1 POVD3L R/W-1 POVD2H R/W-1 POVD2L R/W-1 POVD1H R/W-1 POVD1L bit 8 R/W-0 POUT1L bit 0 POVDxH<4:1>:POVDxL<4:1>: PWM Output Override bits 1 = Output on PWMx I/O pin is controlled by the PWM generator 0 = Output on PWMx I/O pin is controlled by the value in the corresponding POUTxH:POUTxL bit POUTxH<4:1>:POUTxL<4:1>: PWM Manual Output bits 1 = PWMx I/O pin is driven active when the corresponding POVDxH:POVDxL bit is cleared 0 = PWMx I/O pin is driven inactive when the corresponding POVDxH:POVDxL bit is cleared bit 7-0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 193 dsPIC33F REGISTER 15-12: PDC1: PWM DUTY CYCLE REGISTER 1 R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 PDC1<15:8> PDC1<7:0> PDC1<15:0>: PWM Duty Cycle #1 Value bits REGISTER 15-13: PDC2: PWM DUTY CYCLE REGISTER 2 R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 PDC2<15:8> PDC2<7:0> PDC2<15:0>: PWM Duty Cycle #2 Value bits DS70165E-page 194 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 15-14: PDC3: PWM DUTY CYCLE REGISTER 3 R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 PDC3<15:8> PDC3<7:0> PDC3<15:0>: PWM Duty Cycle #3 Value bits REGISTER 15-15: PDC4: PWM DUTY CYCLE REGISTER 4 R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 PDC4<15:8> PDC4<7:0> PDC4<15:0>: PWM Duty Cycle #4 Value bits (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 195 dsPIC33F NOTES: DS70165E-page 196 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 16.0 Note: QUADRATURE ENCODER INTERFACE (QEI) MODULE This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). The operational features of the QEI include: * Three input channels for two phase signals and index pulse * 16-bit up/down position counter * Count direction status * Position Measurement (x2 and x4) mode * Programmable digital noise filters on inputs * Alternate 16-bit Timer/Counter mode * Quadrature Encoder Interface interrupts These operating modes are determined by setting the appropriate bits, QEIM<2:0> (QEICON<10:8>). Figure 16-1 depicts the Quadrature Encoder Interface block diagram. This section describes the Quadrature Encoder Interface (QEI) module and associated operational modes. The QEI module provides the interface to incremental encoders for obtaining mechanical position data. FIGURE 16-1: Sleep Input QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM TQCKPS<1:0> TQCS TCY 0 1 QEIM<2:0> 1 Prescaler 1, 8, 64, 256 2 Synchronize Det 0 QEIIF Event Flag TQGATE D CK Q Q QEA Programmable Digital Filter UPDN_SRC 0 1 QEICON<11> 2 Quadrature Encoder Interface Logic 16-bit Up/Down Counter (POSCNT) Reset Comparator/ Zero Detect Equal 3 QEIM<2:0> Mode Select Max Count Register (MAXCNT) QEB Programmable Digital Filter INDX Programmable Digital Filter 3 PCDOUT Existing Pin Logic Up/Down 0 UPDN 1 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 197 dsPIC33F 16.1 Quadrature Encoder Interface Logic If the POSRES bit is set to `1', then the position counter is reset when the index pulse is detected. If the POSRES bit is set to `0', then the position counter is not reset when the index pulse is detected. The position counter will continue counting up or down, and will be reset on the rollover or underflow condition. The interrupt is still generated on the detection of the index pulse and not on the position counter overflow/ underflow. A typical incremental (a.k.a. optical) encoder has three outputs: Phase A, Phase B and an index pulse. These signals are useful and often required in position and speed control of ACIM and SR motors. The two channels, Phase A (QEA) and Phase B (QEB), have a unique relationship. If Phase A leads Phase B, then the direction (of the motor) is deemed positive or forward. If Phase A lags Phase B, then the direction (of the motor) is deemed negative or reverse. A third channel, termed index pulse, occurs once per revolution and is used as a reference to establish an absolute position. The index pulse coincides with Phase A and Phase B, both low. 16.2.3 COUNT DIRECTION STATUS 16.2 16-bit Up/Down Position Counter Mode As mentioned in the previous section, the QEI logic generates a UPDN signal, based upon the relationship between Phase A and Phase B. In addition to the output pin, the state of this internal UPDN signal is supplied to an SFR bit, UPDN (QEICON<11>), as a read-only bit. To place the state of this signal on an I/O pin, the SFR bit, PCDOUT (QEICON<6>), must be set to `1'. The 16-bit up/down counter counts up or down on every count pulse, which is generated by the difference of the Phase A and Phase B input signals. The counter acts as an integrator whose count value is proportional to position. The direction of the count is determined by the UPDN signal which is generated by the Quadrature Encoder Interface logic. 16.3 Position Measurement Mode There are two measurement modes which are supported and are termed x2 and x4. These modes are selected by the QEIM<2:0> mode select bits located in SFR QEICON<10:8>. When control bits, QEIM<2:0> = 100 or 101, the x2 Measurement mode is selected and the QEI logic only looks at the Phase A input for the position counter increment rate. Every rising and falling edge of the Phase A signal causes the position counter to be incremented or decremented. The Phase B signal is still utilized for the determination of the counter direction, just as in the x4 Measurement mode. Within the x2 Measurement mode, there are two variations of how the position counter is reset: 1. 2. Position counter reset by detection of index pulse, QEIM<2:0> = 100. Position counter reset by match with MAXCNT, QEIM<2:0> = 101. 16.2.1 POSITION COUNTER ERROR CHECKING Position counter error checking in the QEI is provided for and indicated by the CNTERR bit (QEICON<15>). The error checking only applies when the position counter is configured for Reset on the Index Pulse modes (QEIM<2:0> = 110 or 100). In these modes, the contents of the POSCNT register are compared with the values (0xFFFF or MAXCNT + 1, depending on direction). If these values are detected, an error condition is generated by setting the CNTERR bit and a QEI counter error interrupt is generated. The QEI counter error interrupt can be disabled by setting the CEID bit (DFLTCON<8>). The position counter continues to count encoder edges after an error has been detected. The POSCNT register continues to count up/down until a natural rollover/underflow. No interrupt is generated for the natural rollover/underflow event. The CNTERR bit is a read/write bit and is reset in software by the user. When control bits, QEIM<2:0> = 110 or 111, the x4 Measurement mode is selected and the QEI logic looks at both edges of the Phase A and Phase B input signals. Every edge of both signals causes the position counter to increment or decrement. Within the x4 Measurement mode, there are two variations of how the position counter is reset: 1. 2. Position counter reset by detection of index pulse, QEIM<2:0> = 110. Position counter reset by match with MAXCNT, QEIM<2:0> = 111. 16.2.2 POSITION COUNTER RESET The Position Counter Reset Enable bit, POSRES (QEI<2>), controls whether the position counter is reset when the index pulse is detected. This bit is only applicable when QEIM<2:0> = 100 or 110. The x4 Measurement mode provides for finer resolution data (more position counts) for determining motor position. DS70165E-page 198 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 16.4 Programmable Digital Noise Filters In addition, control bit UPDN_SRC, (QEICON<0>), determines whether the timer count direction state is based on the logic state written into the UPDN control/ status bit (QEICON<11>) or the QEB pin state. When UPDN_SRC = 1, the timer count direction is controlled from the QEB pin. Likewise, when UPDN_SRC = 0, the timer count direction is controlled by the UPDN bit. Note: This timer does not support the External Asynchronous Counter mode of operation. If using an external clock source, the clock will automatically be synchronized to the internal instruction cycle. The digital noise filter section is responsible for rejecting noise on the incoming capture or quadrature signals. Schmitt Trigger inputs and a 3-clock cycle delay filter combine to reject low-level noise and large, short duration noise spikes that typically occur in noise prone applications, such as a motor system. The filter ensures that the filtered output signal is not permitted to change until a stable value has been registered for three consecutive clock cycles. For the QEA, QEB and INDX pins, the clock divide frequency for the digital filter is programmed by bits, QECK<2:0> (DFLTCON<6:4>), and are derived from the base instruction cycle, TCY. To enable the filter output for channels QEA, QEB and INDX, the QEOUT bit must be `1'. The filter network for all channels is disabled on POR. 16.6 16.6.1 QEI Module Operation During CPU Sleep Mode QEI OPERATION DURING CPU SLEEP MODE 16.5 Alternate 16-bit Timer/Counter The QEI module will be halted during the CPU Sleep mode. When the QEI module is not configured for the QEI mode, QEIM<2:0> = 001, the module can be configured as a simple 16-bit timer/counter. The setup and control of the auxiliary timer is accomplished through the QEICON SFR register. This timer functions identically to Timer1. The QEA pin is used as the timer clock input. When configured as a timer, the POSCNT register serves as the Timer Count register and the MAXCNT register serves as the Period register. When a Timer/ Period register match occur, the QEI interrupt flag will be asserted. The only exception between the general purpose timers and this timer is the added feature of external up/down input select. When the UPDN pin is asserted high, the timer will increment up. When the UPDN pin is asserted low, the timer will be decremented. Note: Changing the operational mode (i.e., from QEI to timer or vice versa) will not affect the Timer/Position Count register contents. 16.6.2 TIMER OPERATION DURING CPU SLEEP MODE During CPU Sleep mode, the timer will not operate because the internal clocks are disabled. 16.7 QEI Module Operation During CPU Idle Mode Since the QEI module can function as a Quadrature Encoder Interface, or as a 16-bit timer, the following section describes operation of the module in both modes. 16.7.1 QEI OPERATION DURING CPU IDLE MODE When the CPU is placed in the Idle mode, the QEI module will operate if QEISIDL (QEICON<13>) = 0. This bit defaults to a logic `0' upon executing POR. For halting the QEI module during the CPU Idle mode, QEISIDL should be set to `1'. The UPDN control/status bit (QEICON<11>) can be used to select the count direction state of the Timer register. When UPDN = 1, the timer will count up. When UPDN = 0, the timer will count down. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 199 dsPIC33F 16.7.2 TIMER OPERATION DURING CPU IDLE MODE 16.9 Control and Status Registers When the CPU is placed in the Idle mode and the QEI module is configured in the 16-bit Timer mode, the 16-bit timer will operate if QEISIDL (QEICON<13>) = 0. This bit defaults to a logic `0' upon executing POR. For halting the timer module during the CPU Idle mode, QEISIDL should be set to `1'. If the QEISIDL bit is cleared, the timer will function normally as if the CPU Idle mode had not been entered. The QEI module has four user-accessible registers. The registers are accessible in either Byte or Word mode. These registers are: * Control/Status Register (QEICON) - This register allows control of the QEI operation and status flags indicating the module state. * Digital Filter Control Register (DFLTCON) - This register allows control of the digital input filter operation. * Position Count Register (POSCNT) - This location allows reading and writing of the 16-bit position counter. * Maximum Count Register (MAXCNT) - The MAXCNT register holds a value that will be compared to the POSCNT counter in some operations. Note: The POSCNT register allows byte accesses, however, reading the register in byte mode may result in partially updated values in subsequent reads. Either use Word mode reads/writes or ensure that the counter is not counting during byte operations. 16.8 Quadrature Encoder Interface Interrupts The Quadrature Encoder Interface has the ability to generate an interrupt on occurrence of the following events: * Interrupt on 16-bit up/down position counter rollover/underflow * Detection of qualified index pulse or if CNTERR bit is set * Timer period match event (overflow/underflow) * Gate accumulation event The QEI Interrupt Flag bit, QEIIF, is asserted upon occurrence of any of the above events. The QEIIF bit must be cleared in software. QEIIF is located in the IFS3 register. Enabling an interrupt is accomplished via the respective enable bit, QEIIE. The QEIIE bit is located in the IEC3 register. DS70165E-page 200 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 16-1: R/W-0 CNTERR bit 15 R/W-0 SWPAB bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 PCDOUT R/W-0 TQGATE R/W-0 R/W-0 R/W-0 POSRES R/W-0 TQCS QEICON: QEI CONTROL REGISTER U-0 -- R/W-0 QEISIDL R-0 INDEX R/W-0 UPDN R/W-0 R/W-0 QEIM<2:0> bit 8 R/W-0 UPDN_SRC bit 0 R/W-0 TQCKPS<1:0> CNTERR: Count Error Status Flag bit 1 = Position count error has occurred 0 = No position count error has occurred (CNTERR flag only applies when QEIM<2:0> = `110' or `100') Unimplemented: Read as `0' QEISIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode INDEX: Index Pin State Status bit (Read-Only) 1 = Index pin is High 0 = Index pin is Low UPDN: Position Counter Direction Status bit 1 = Position Counter Direction is positive (+) 0 = Position Counter Direction is negative (-) (Read-only bit when QEIM<2:0> = `1XX') (Read/Write bit when QEIM<2:0> = `001') QEIM<2:0>: Quadrature Encoder Interface Mode Select bits 111 = Quadrature Encoder Interface enabled (x4 mode) with position counter reset by match (MAXCNT) 110 = Quadrature Encoder Interface enabled (x4 mode) with Index Pulse reset of position counter 101 = Quadrature Encoder Interface enabled (x2 mode) with position counter reset by match (MAXCNT) 100 = Quadrature Encoder Interface enabled (x2 mode) with Index Pulse reset of position counter 011 = Unused (Module disabled) 010 = Unused (Module disabled) 001 = Starts 16-bit Timer 000 = Quadrature Encoder Interface/Timer off SWPAB: Phase A and Phase B Input Swap Select bit 1 = Phase A and Phase B inputs swapped 0 = Phase A and Phase B inputs not swapped PCDOUT: Position Counter Direction State Output Enable bit 1 = Position Counter Direction Status Output Enable (QEI logic controls state of I/O pin) 0 = Position Counter Direction Status Output Disabled (Normal I/O pin operation) TQGATE: Timer Gated Time Accumulation Enable bit 1 = Timer gated time accumulation enabled 0 = Timer gated time accumulation disabled bit 14 bit 13 bit 12 bit 11 bit 10-8 bit 7 bit 6 bit 5 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 201 dsPIC33F REGISTER 16-1: bit 4-3 QEICON: QEI CONTROL REGISTER (CONTINUED) TQCKPS<1:0>: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value (Prescaler utilized for 16-bit Timer mode only) POSRES: Position Counter Reset Enable bit 1 = Index Pulse resets Position Counter 0 = Index Pulse does not reset Position Counter (Bit only applies when QEIM<2:0> = 100 or 110) TQCS: Timer Clock Source Select bit 1 = External clock from pin QEA (on the rising edge) 0 = Internal clock (TCY) UPDN_SRC: Position Counter Direction Selection Control bit 1 = QEB pin State Defines Position Counter Direction 0 = Control/Status bit, UPDN (QEICON<11>), Defines Timer Counter (POSCNT) direction Note: When configured for QEI mode, control bit is a `don't care'. bit 2 bit 1 bit 0 DS70165E-page 202 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 16-2: U-0 -- bit 15 R/W-0 QEOUT bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-9 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 QECK<2:0> U-0 -- U-0 -- U-0 -- U-0 -- bit 0 DFLTCON: DIGITAL FILTER CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 CEID bit 8 IMV<2:0> Unimplemented: Read as `0' IMV<1:0>: Index Match Value bits - These bits allow the user to specify the state of the QEA and QEB input pins during an Index pulse when the POSCNT register is to be reset. In 4X Quadrature Count Mode: IMV1= Required State of Phase B input signal for match on index pulse IMV0= Required State of Phase A input signal for match on index pulse In 2X Quadrature Count Mode: IMV1= Selects Phase input signal for Index state match (0 = Phase A, 1 = Phase B) IMV0= Required State of the selected Phase input signal for match on index pulse CEID: Count Error Interrupt Disable bit 1 = Interrupts due to count errors are disabled 0 = Interrupts due to count errors are enabled QEOUT: QEA/QEB/INDX Pin Digital Filter Output Enable bit 1 = Digital filter outputs enabled 0 = Digital filter outputs disabled (normal pin operation) QECK<2:0>: QEA/QEB/INDX Digital Filter Clock Divide Select Bits 111 = 1:256 Clock Divide 110 = 1:128 Clock Divide 101 = 1:64 Clock Divide 100 = 1:32 Clock Divide 011 = 1:16 Clock Divide 010 = 1:4 Clock Divide 001 = 1:2 Clock Divide 000 = 1:1 Clock Divide Unimplemented: Read as `0' bit 8 bit 7 bit 6-4 bit 3-0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 203 dsPIC33F NOTES: DS70165E-page 204 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 17.0 Note: SERIAL PERIPHERAL INTERFACE (SPI) This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). buffer are moved to SPIxSR. The received data is thus placed in SPIxBUF and the transmit data in SPIxSR is ready for the next transfer. Note: Both the transmit buffer (SPIxTXB) and the receive buffer (SPIxRXB) are mapped to the same register address, SPIxBUF. Do not perform read-modify-write operations (such as bit-oriented instructions) on the SPIxBUF register. The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, ADC, etc. The SPI module is compatible with SPI and SIOP from Motorola(R). Note: In this section, the SPI modules are referred to together as SPIx, or separately as SPI1 and SPI2. Special Function Registers will follow a similar notation. For example, SPIxCON refers to the control register for the SPI1 or SPI2 module. To set up the SPI module for the Master mode of operation: 1. If using interrupts: a) Clear the SPIxIF bit in the respective IFSn register. b) Set the SPIxIE bit in the respective IECn register. c) Write the SPIxIP bits in the respective IPCn register to set the interrupt priority. Write the desired settings to the SPIxCON register with MSTEN (SPIxCON1<5>) = 1. Clear the SPIROV bit (SPIxSTAT<6>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). Write the data to be transmitted to the SPIxBUF register. Transmission (and reception) will start as soon as data is written to the SPIxBUF register. Clear the SPIxBUF register. If using interrupts: a) Clear the SPIxIF bit in the respective IFSn register. b) Set the SPIxIE bit in the respective IECn register. c) Write the SPIxIP bits in the respective IPCn register to set the interrupt priority. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 0. Clear the SMP bit. If the CKE bit is set, then the SSEN bit (SPIxCON1<7>) must be set to enable the SSx pin. Clear the SPIROV bit (SPIxSTAT<6>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). 2. 3. 4. 5. Each SPI module consists of a 16-bit shift register, SPIxSR (where x = 1 or 2), used for shifting data in and out, and a buffer register, SPIxBUF. A control register, SPIxCON, configures the module. Additionally, a status register, SPIxSTAT, indicates various status conditions. The serial interface consists of 4 pins: SDIx (serial data input), SDOx (serial data output), SCKx (shift clock input or output), and SSx (active low slave select). In Master mode operation, SCK is a clock output but in Slave mode, it is a clock input. A series of eight (8) or sixteen (16) clock pulses shift out bits from the SPIxSR to SDOx pin and simultaneously shift in data from SDIx pin. An interrupt is generated when the transfer is complete and the corresponding interrupt flag bit (SPI1IF or SPI2IF) is set. This interrupt can be disabled through an interrupt enable bit (SPI1IE or SPI2IE). The receive operation is double-buffered. When a complete byte is received, it is transferred from SPIxSR to SPIxBUF. If the receive buffer is full when new data is being transferred from SPIxSR to SPIxBUF, the module will set the SPIROV bit indicating an overflow condition. The transfer of the data from SPIxSR to SPIxBUF will not be completed and the new data will be lost. The module will not respond to SCL transitions while SPIROV is `1', effectively disabling the module until SPIxBUF is read by user software. Transmit writes are also double-buffered. The user writes to SPIxBUF. When the master or slave transfer is completed, the contents of the shift register (SPIxSR) are moved to the receive buffer. If any transmit data has been written to the buffer register, the contents of the transmit To set up the SPI module for the Slave mode of operation: 1. 2. 3. 4. 5. 6. 7. The SPI module generates an interrupt indicating completion of a byte or word transfer, as well as a separate interrupt for all SPI error conditions. Note: Both SPI1 and SPI2 can trigger a DMA data transfer. If SPI1 or SPI2 is selected as the DMA IRQ source, a DMA transfer occurs when the SPI1IF or SPI2IF bit gets set as a result of an SPI1 or SPI2 byte or word transfer. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 205 dsPIC33F FIGURE 17-1: SCKx SPI MODULE BLOCK DIAGRAM 1:1 to 1:8 Secondary Prescaler Sync Control Control Clock Shift Control Select Edge 1:1/4/16/64 Primary Prescaler FCY SSx SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock SPIxSR SDOx SDIx bit 0 Transfer Transfer SPIxRXB SPIxTXB SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus DS70165E-page 206 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F FIGURE 17-2: SPI MASTER/SLAVE CONNECTION PROCESSOR 1 (SPI Master) PROCESSOR 2 (SPI Slave) SDOx SDIx Serial Receive Buffer (SPIxRXB) Serial Receive Buffer (SPIxRXB) Shift Register (SPIxSR) MSb LSb SDIx SDOx MSb Shift Register (SPIxSR) LSb Serial Transmit Buffer (SPIxTXB) Serial Transmit Buffer (SPIxTXB) SPI Buffer (SPIxBUF)(2) SCKx Serial Clock SCKx SPI Buffer (SPIxBUF)(2) SSx(1) (MSTEN (SPIxCON1<5>) = 1) Note (SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0) 1:Using the SSx pin in Slave mode of operation is optional. 2: User must write transmit data to/read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF. FIGURE 17-3: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM dsPIC33F (SPI Slave, Frame Slave) SDOx SDIx PROCESSOR 2 SDIx SCKx SSx Frame Sync Pulse Serial Clock SDOx SCKx SSx FIGURE 17-4: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM dsPIC33F (SPI Master, Frame Slave) SDOx SDIx SCKx SSx Frame Sync Pulse Serial Clock SDIx SDOx SCKx SSx PROCESSOR 2 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 207 dsPIC33F FIGURE 17-5: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM dsPIC33F (SPI Slave, Frame Slave) SDOx SDIx PROCESSOR 2 SDIx Serial Clock SCKx SSx Frame Sync Pulse SDOx SCKx SSx FIGURE 17-6: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM dsPIC33F (SPI Master, Frame Slave) SDOx SDIx PROCESSOR 2 SDIx Serial Clock SCKx SSx Frame Sync Pulse SDOx SCKx SSx EQUATION 17-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED FSCK = FCY Primary Prescaler * Secondary Prescaler TABLE 17-1: SAMPLE SCKx FREQUENCIES Secondary Prescaler Settings FCY = 40 MHz 1:1 2:1 Invalid 5000 1250 312.5 4:1 10000 2500 625 156.25 6:1 6666.67 1666.67 416.67 104.17 8:1 5000 1250 312.50 78.125 Primary Prescaler Settings 1:1 4:1 16:1 64:1 Invalid 10000 2500 625 FCY = 5 MHz Primary Prescaler Settings 1:1 4:1 16:1 64:1 Note: SCKx frequencies shown in kHz. 5000 1250 313 78 2500 625 156 39 1250 313 78 20 833 208 52 13 625 156 39 10 DS70165E-page 208 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 17-1: R/W-0 SPIEN bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/C-0 SPIROV U-0 -- U-0 -- U-0 -- U-0 -- R-0 SPITBF R-0 SPIRBF bit 0 SPIxSTAT: SPIx STATUS AND CONTROL REGISTER U-0 -- R/W-0 SPISIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 SPIEN: SPIx Enable bit 1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables module Unimplemented: Read as `0' SPISIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' SPIROV: Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded. The user software has not read the previous data in the SPIxBUF register. 0 = No overflow has occurred Unimplemented: Read as `0' SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR. SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. bit 14 bit 13 bit 12-7 bit 6 bit 5-2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 209 dsPIC33F REGISTER 17-2: U-0 -- bit 15 R/W-0 SSEN bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 CKP R/W-0 MSTEN R/W-0 R/W-0 SPRE<2:0> R/W-0 R/W-0 SPIXCON1: SPIx CONTROL REGISTER 1 U-0 -- U-0 -- R/W-0 DISSCK R/W-0 DISSDO R/W-0 MODE16 R/W-0 SMP R/W-0 CKE(1) bit 8 R/W-0 bit 0 PPRE<1:0> Unimplemented: Read as `0' DISSCK: Disable SCKx pin bit (SPI Master modes only) 1 = Internal SPI clock is disabled, pin functions as I/O 0 = Internal SPI clock is enabled DISSDO: Disable SDOx pin bit 1 = SDOx pin is not used by module; pin functions as I/O 0 = SDOx pin is controlled by the module MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. CKE: SPIx Clock Edge Select bit(1) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) SSEN: Slave Select Enable bit (Slave mode) 1 = SSx pin used for Slave mode 0 = SSx pin not used by module. Pin controlled by port function. CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode SPRE<2:0>: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 ... 000 = Secondary prescale 8:1 PPRE<1:0>: Primary Prescale bits (Master mode) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 The CKE bit is not used in the Framed SPI modes. The user should program this bit to `0' for the Framed SPI modes (FRMEN = 1). bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4-2 bit 1-0 Note 1: DS70165E-page 210 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 17-3: R/W-0 FRMEN bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 FRMDLY U-0 -- bit 0 SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 FRMPOL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 SPIFSD FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output) 0 = Framed SPIx support disabled SPIFSD: Frame Sync Pulse Direction Control bit 1 = Frame sync pulse input (slave) 0 = Frame sync pulse output (master) FRMPOL: Frame Sync Pulse Polarity bit 1 = Frame sync pulse is active-high 0 = Frame sync pulse is active-low Unimplemented: Read as `0' FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock Unimplemented: This bit must not be set to `1' by the user application. bit 14 bit 13 bit 12-2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 211 dsPIC33F NOTES: DS70165E-page 212 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 18.0 Note: INTER-INTEGRATED CIRCUIT (I2C) This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). 18.2 I2C Registers I2CxCON and I2CxSTAT are control and status registers, respectively. The I2CxCON register is readable and writable. The lower six bits of I2CxSTAT are read-only. The remaining bits of the I2CSTAT are read/write. I2CxRSR is the shift register used for shifting data, whereas I2CxRCV is the buffer register to which data bytes are written, or from which data bytes are read. I2CxRCV is the receive buffer. I2CxTRN is the transmit register to which bytes are written during a transmit operation. The I2CxADD register holds the slave address. A status bit, ADD10, indicates 10-bit Address mode. The I2CxBRG acts as the Baud Rate Generator (BRG) reload value. In receive operations, I2CxRSR and I2CxRCV together form a double-buffered receiver. When I2CxRSR receives a complete byte, it is transferred to I2CxRCV and an interrupt pulse is generated. The Inter-Integrated Circuit (I2C) module provides complete hardware support for both Slave and MultiMaster modes of the I2C serial communication standard, with a 16-bit interface. The dsPIC33F devices have up to two I2C interface modules, denoted as I2C1 and I2C2. Each I2C module has a 2-pin interface: the SCLx pin is clock and the SDAx pin is data. Each I2C module `x' (x = 1 or 2) offers the following key features: * I2C interface supporting both master and slave operation. * I2C Slave mode supports 7 and 10-bit address. * I2C Master mode supports 7 and 10-bit address. * I2C port allows bidirectional transfers between master and slaves. * Serial clock synchronization for I2C port can be used as a handshake mechanism to suspend and resume serial transfer (SCLREL control). * I2C supports multi-master operation; detects bus collision and will arbitrate accordingly. 18.3 I2C Interrupts The I2C module generates two interrupt flags, MI2CxIF (I2C Master Events Interrupt Flag) and SI2CxIF (I2C Slave Events Interrupt Flag). A separate interrupt is generated for all I2C error conditions. 18.4 I2C Baud Rate Generator 18.1 Operating Modes The hardware fully implements all the master and slave functions of the I2C Standard and Fast mode specifications, as well as 7 and 10-bit addressing. module can operate either as a slave or a The I master on an I2C bus. The following types of I2C operation are supported: * * * I2C slave operation with 7-bit address I2C slave operation with 10-bit address I2C master operation with 7 or 10-bit address 2C In Master mode, the reload value for the BRG is located in the I2CxBRG register. When the BRG is loaded with this value, the BRG counts down to `0' and stops until another reload has taken place. If clock arbitration is taking place, for instance, the BRG is reloaded when the SCLx pin is sampled high. As per the I2C standard, FSCL may be 100 kHz or 400 kHz. However, the user can specify any baud rate up to 1 MHz. I2CxBRG values of `0' or `1' are illegal. EQUATION 18-1: I2CxBRG = SERIAL CLOCK RATE FCY ( FSCL - FCY -1 1,111,111 ) For details about the communication sequence in each of these modes, please refer to the "dsPIC30F Family Reference Manual". (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 213 dsPIC33F FIGURE 18-1: I2CTM BLOCK DIAGRAM (X = 1 OR 2) Internal Data Bus I2CxRCV Read SCLx Shift Clock I2CxRSR LSb SDAx Match Detect Address Match Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Read Write Collision Detect I2CxCON Read Acknowledge Generation Clock Stretching Write I2CxTRN LSb Shift Clock Reload Control Read Write I2CxBRG Read BRG Down Counter TCY/2 DS70165E-page 214 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 18.5 I2C Module Addresses 18.8 General Call Address Support The I2CxADD register contains the Slave mode addresses. The register is a 10-bit register. If the A10M bit (I2CxCON<10>) is `0', the address is interpreted by the module as a 7-bit address. When an address is received, it is compared to the 7 Least Significant bits of the I2CxADD register. If the A10M bit is `1', the address is assumed to be a 10-bit address. When an address is received, it will be compared with the binary value, `11110 A9 A8' (where A9 and A8 are two Most Significant bits of I2CxADD). If that value matches, the next address will be compared with the Least Significant 8 bits of I2CxADD, as specified in the 10-bit addressing protocol. The general call address can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledgement. The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It consists of all `0's with R_W = 0. The general call address is recognized when the General Call Enable (GCEN) bit is set (I2CxCON<7> = 1). When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the I2CxRCV to determine if the address was device-specific or a general call address. 18.9 Automatic Clock Stretch TABLE 18-1: 7-BIT I2CTM SLAVE ADDRESSES SUPPORTED BY dsPIC33F General call address or Start byte Reserved Hs mode Master codes Valid 7-bit addresses Valid 10-bit addresses (lower 7 bits) Reserved In Slave modes, the module can synchronize buffer reads and write to the master device by clock stretching. 18.9.1 TRANSMIT CLOCK STRETCHING 0x00 0x01-0x03 0x04-0x07 0x08-0x77 0x78-0x7b 0x7c-0x7f Both 10-bit and 7-bit Transmit modes implement clock stretching by asserting the SCLREL bit after the falling edge of the ninth clock, if the TBF bit is cleared, indicating the buffer is empty. In Slave Transmit modes, clock stretching is always performed, irrespective of the STREN bit. The user's ISR must set the SCLREL bit before transmission is allowed to continue. By holding the SCLx line low, the user has time to service the ISR and load the contents of the I2CxTRN before the master device can initiate another transmit sequence. 18.6 Slave Address Masking The I2CxMSK register (Register 18-3) designates address bit positions as "don't care" for both 7-bit and 10-bit Address modes. Setting a particular bit location (= 1) in the I2CxMSK register, causes the slave module to respond, whether the corresponding address bit value is a `0' or `1'. For example, when I2CxMSK is set to `00100000', the slave module will detect both addresses, `0000000' and `00100000'. To enable address masking, the IPMI (Intelligent Peripheral Management Interface) must be disabled by clearing the IPMIEN bit (I2CxCON<11>). 18.9.2 RECEIVE CLOCK STRETCHING The STREN bit in the I2CxCON register can be used to enable clock stretching in Slave Receive mode. When the STREN bit is set, the SCLx pin will be held low at the end of each data receive sequence. The user's ISR must set the SCLREL bit before reception is allowed to continue. By holding the SCLx line low, the user has time to service the ISR and read the contents of the I2CxRCV before the master device can initiate another receive sequence. This will prevent buffer overruns from occurring. 18.7 IPMI Support The control bit, IPMIEN, enables the module to support the Intelligent Peripheral Management Interface (IPMI). When this bit is set, the module accepts and acts upon all addresses. 18.10 Software Controlled Clock Stretching (STREN = 1) When the STREN bit is `1', the SCLREL bit may be cleared by software to allow software to control the clock stretching. If the STREN bit is `0', a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 215 dsPIC33F 18.11 Slope Control The I C standard requires slope control on the SDAx and SCLx signals for Fast mode (400 kHz). The control bit, DISSLW, enables the user to disable slew rate control if desired. It is necessary to disable the slew rate control for 1 MHz mode. 2 18.13 Multi-Master Communication, Bus Collision and Bus Arbitration Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master outputs a `1' on SDAx by letting SDAx float high while another master asserts a `0'. When the SCLx pin floats high, data should be stable. If the expected data on SDAx is a `1' and the data sampled on the SDAx pin = 0, then a bus collision has taken place. The master will set the I2C master events interrupt flag and reset the master portion of the I2C port to its Idle state. 18.12 Clock Arbitration Clock arbitration occurs when the master deasserts the SCLx pin (SCLx allowed to float high) during any receive, transmit or Restart/Stop condition. When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of I2CxBRG and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device. DS70165E-page 216 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 18-1: R/W-0 I2CEN bit 15 R/W-0 GCEN bit 7 Legend: R = Readable bit -n = Value at POR bit 15 U = Unimplemented bit, read as `0' W = Writable bit `1' = Bit is set HS = Set in hardware `0' = Bit is cleared HC = Cleared in hardware x = Bit is unknown R/W-0 STREN R/W-0 ACKDT R/W-0 HC ACKEN R/W-0 HC RCEN R/W-0 HC PEN R/W-0 HC RSEN I2CxCON: I2Cx CONTROL REGISTER U-0 -- R/W-0 I2CSIDL R/W-1 HC SCLREL R/W-0 IPMIEN R/W-0 A10M R/W-0 DISSLW R/W-0 SMEN bit 8 R/W-0 HC SEN bit 0 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module. All I2C pins are controlled by port functions. Unimplemented: Read as `0' I2CSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters an Idle mode 0 = Continue module operation in Idle mode SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Release SCLx clock 0 = Hold SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software may write `0' to initiate stretch and write `1' to release clock). Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software may only write `1' to release clock). Hardware clear at beginning of slave transmission. IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit 1 = IPMI mode is enabled; all addresses Acknowledged 0 = IPMI mode disabled A10M: 10-bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled SMEN: SMBus Input Levels bit 1 = Enable I/O pin thresholds compliant with SMBus specification 0 = Disable SMBus input thresholds GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit. 1 = Enable software or receive clock stretching 0 = Disable software or receive clock stretching bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 217 dsPIC33F REGISTER 18-1: bit 5 I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that will be transmitted when the software initiates an Acknowledge sequence. 1 = Send NACK during Acknowledge 0 = Send ACK during Acknowledge ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardware clear at end of master Acknowledge sequence. 0 = Acknowledge sequence not in progress RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte. 0 = Receive sequence not in progress PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence. 0 = Stop condition not in progress RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence. 0 = Repeated Start condition not in progress SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence. 0 = Start condition not in progress bit 4 bit 3 bit 2 bit 1 bit 0 DS70165E-page 218 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 18-2: R-0 HSC ACKSTAT bit 15 R/C-0 HS IWCOL bit 7 Legend: R = Readable bit -n = Value at POR bit 15 U = Unimplemented bit, read as `0' W = Writable bit `1' = Bit is set HS = Set in hardware `0' = Bit is cleared HSC = Hardware set/cleared x = Bit is unknown R/C-0 HS I2COV R-0 HSC D_A R/C-0 HSC P R/C-0 HSC S R-0 HSC R_W R-0 HSC RBF I2CxSTAT: I2Cx STATUS REGISTER U-0 -- U-0 -- U-0 -- R/C-0 HS BCL R-0 HSC GCSTAT R-0 HSC ADD10 bit 8 R-0 HSC TBF bit 0 R-0 HSC TRSTAT ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation) 1 = NACK received from slave 0 = ACK received from slave Hardware set or clear at end of slave Acknowledge. TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge. Unimplemented: Read as `0' BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware set at detection of bus collision. GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware set when address matches general call address. Hardware clear at Stop detection. ADD10: 10-bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection. IWCOL: Write Collision Detect bit 1 = An attempt to write the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware set at occurrence of write to I2CxTRN while busy (cleared by software). I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software). D_A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by reception of slave byte. P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 14 bit 13-11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 219 dsPIC33F REGISTER 18-2: bit 3 I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. R_W: Read/Write Information bit (when operating as I2C slave) 1 = Read - indicates data transfer is output from slave 0 = Write - indicates data transfer is input to slave Hardware set or clear after reception of I 2C device address byte. RBF: Receive Buffer Full Status bit 1 = Receive complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. bit 2 bit 1 bit 0 DS70165E-page 220 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 18-3: U-0 -- bit 15 R/W-0 AMSK7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 AMSK6 R/W-0 AMSK5 R/W-0 AMSK4 R/W-0 AMSK3 R/W-0 AMSK2 R/W-0 AMSK1 I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 AMSK9 R/W-0 AMSK8 bit 8 R/W-0 AMSK0 bit 0 Unimplemented: Read as `0' AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 221 dsPIC33F NOTES: DS70165E-page 222 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 19.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). * Fully Integrated Baud Rate Generator with 16-bit Prescaler * Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS * 4-deep First-In-First-Out (FIFO) Transmit Data Buffer * 4-Deep FIFO Receive Data Buffer * Parity, Framing and Buffer Overrun Error Detection * Support for 9-bit mode with Address Detect (9th bit = 1) * Transmit and Receive Interrupts * A Separate Interrupt for all UART Error Conditions * Loopback mode for Diagnostic Support * Support for Sync and Break Characters * Supports Automatic Baud Rate Detection * IrDA Encoder and Decoder Logic * 16x Baud Clock Output for IrDA Support A simplified block diagram of the UART is shown in Figure 19-1. The UART module consists of the key important hardware elements: * Baud Rate Generator * Asynchronous Transmitter * Asynchronous Receiver Note: The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the dsPIC33F device family. The UART is a fullduplex asynchronous system that can communicate with peripheral devices, such as personal computers, LIN, RS-232 and RS-485 interfaces. The module also supports a hardware flow control option with the UxCTS and UxRTS pins and also includes an IrDA(R) encoder and decoder. The primary features of the UART module are: * Full-Duplex, 8 or 9-bit Data Transmission through the UxTX and UxRX pins * Even, Odd or No Parity Options (for 8-bit data) * One or Two Stop bits * Hardware Flow Control Option with UxCTS and UxRTS pins FIGURE 19-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA(R) BCLK Hardware Flow Control UxRTS UxCTS UART Receiver UxRX UART Transmitter UxTX Note 1: Both UART1 and UART2 can trigger a DMA data transfer. If U1TX, U1RX, U2TX or U2RX is selected as a DMA IRQ source, a DMA transfer occurs when the U1TXIF, U1RXIF, U2TXIF or U2RXIF bit gets set as a result of a UART1 or UART2 transmission or reception. 2: If DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word (i.e., UTXISEL<1:0> = 00 and URXISEL<1:0> = 00). (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 223 dsPIC33F 19.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator. The BRGx register controls the period of a free-running 16-bit timer. Equation 19-1 shows the formula for computation of the baud rate with BRGH = 0. Equation 19-2 shows the formula for computation of the baud rate with BRGH = 1. EQUATION 19-2: UART BAUD RATE WITH BRGH = 1 FCY 4 * (BRGx + 1) Baud Rate = EQUATION 19-1: UART BAUD RATE WITH BRGH = 0 BRGx = Note: FCY Baud Rate = 16 * (BRGx + 1) FCY -1 BRGx = 16 * Baud Rate Note: FCY denotes the instruction cycle clock frequency (FOSC/2). FCY -1 4 * Baud Rate FCY denotes the instruction cycle clock frequency (FOSC/2). The maximum baud rate (BRGH = 1) possible is FCY/4 (for BRGx = 0), and the minimum baud rate possible is FCY/(4 * 65536). Writing a new value to the BRGx register causes the BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate. Example 19-1 shows the calculation of the baud rate error for the following conditions: * FCY = 4 MHz * Desired Baud Rate = 9600 The maximum baud rate (BRGH = 0) possible is FCY/16 (for BRGx = 0), and the minimum baud rate possible is FCY/(16 * 65536). EXAMPLE 19-1: Desired Baud Rate BAUD RATE ERROR CALCULATION (BRGH = 0) = = = = = = = = = FCY/(16 (BRGx + 1)) ((FCY/Desired Baud Rate)/16) - 1 ((4000000/9600)/16) - 1 25 4000000/(16 (25 + 1)) 9615 (Calculated Baud Rate - Desired Baud Rate) Desired Baud Rate (9615 - 9600)/9600 0.16% Solving for BRGx Value: BRGx BRGx BRGx Calculated Baud Rate Error DS70165E-page 224 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 19.2 1. Transmitting in 8-bit Data Mode 19.5 1. 2. 3. 2. 3. 4. 5. 6. Set up the UART: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the BRGx register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UART. Set the UTXEN bit (causes a transmit interrupt). Write data byte to lower byte of UxTXREG word. The value will be immediately transferred to the Transmit Shift Register (TSR) and the serial bit stream will start shifting out with the next rising edge of the baud clock. Alternately, the data byte may be transferred while UTXEN = 0, and then the user may set UTXEN. This will cause the serial bit stream to begin immediately because the baud clock will start from a cleared state. A transmit interrupt will be generated as per interrupt control bits, UTXISEL<1:0>. Receiving in 8-bit or 9-bit Data Mode 4. 5. Set up the UART (as described in Section 19.2 "Transmitting in 8-bit Data Mode"). Enable the UART. A receive interrupt will be generated when one or more data characters have been received as per interrupt control bits, URXISEL<1:0>. Read the OERR bit to determine if an overrun error has occurred. The OERR bit must be reset in software. Read UxRXREG. The act of reading the UxRXREG character will move the next character to the top of the receive FIFO, including a new set of PERR and FERR values. 19.6 Flow Control Using UxCTS and UxRTS Pins 19.3 1. 2. 3. 4. 5. Transmitting in 9-bit Data Mode 6. Set up the UART (as described in Section 19.2 "Transmitting in 8-bit Data Mode"). Enable the UART. Set the UTXEN bit (causes a transmit interrupt). Write UxTXREG as a 16-bit value only. A word write to UxTXREG triggers the transfer of the 9-bit data to the TSR. Serial bit stream will start shifting out with the first rising edge of the baud clock. A transmit interrupt will be generated as per the setting of control bits, UTXISEL<1:0>. UARTx Clear to Send (UxCTS) and Request to Send (UxRTS) are the two hardware controlled active-low pins that are associated with the UART module. These two pins allow the UART to operate in Simplex and Flow Control modes. They are implemented to control the transmission and the reception between the Data Terminal Equipment (DTE). The UEN<1:0> bits in the UxMODE register configures these pins. 19.7 Infrared Support The UART module provides two types of infrared UART support: * IrDA clock output to support external IrDA encoder and decoder device (legacy module support) * Full implementation of the IrDA encoder and decoder. 19.4 Break and Sync Transmit Sequence 19.7.1 EXTERNAL IrDA SUPPORT - IrDA CLOCK OUTPUT The following sequence will send a message frame header made up of a Break, followed by an auto-baud Sync byte. 1. 2. 3. Configure the UART for the desired mode. Set UTXEN and UTXBRK - sets up the Break character. Load the UxTXREG register with a dummy character to initiate transmission (value is ignored). Write 0x55 to UxTXREG - loads Sync character into the transmit FIFO. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. To support external IrDA encoder and decoder devices, the BCLK pin (same as the UxRTS pin) can be configured to generate the 16x baud clock. With UEN<1:0> = 11, the BCLK pin will output the 16x baud clock if the UART module is enabled; it can be used to support the IrDA codec chip. 19.7.2 BUILT-IN IrDA ENCODER AND DECODER 4. 5. The UART has full implementation of the IrDA encoder and decoder as part of the UART module. The built-in IrDA encoder and decoder functionality is enabled using the IREN bit (UxMODE<12>). When enabled (IREN = 1), the receive pin (UxRX) acts as the input from the infrared receiver. The transmit pin (UxTX) acts as the output to the infrared transmitter. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 225 dsPIC33F REGISTER 19-1: R/W-0 UARTEN bit 15 R/W-0 HC WAKE bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HC = Hardware cleared W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 LPBACK R/W-0 HC ABAUD R/W-0 URXINV R/W-0 BRGH R/W-0 R/W-0 UxMODE: UARTx MODE REGISTER U-0 -- R/W-0 USIDL R/W-0 IREN (1) R/W-0 RTSMD U-0 -- R/W-0(2) R/W-0(2) bit 8 R/W-0 STSEL bit 0 UEN<1:0> PDSEL<1:0> UARTEN: UARTx Enable bit 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> 0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption minimal Unimplemented: Read as `0' USIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode. 0 = Continue module operation in Idle mode IREN: IrDA Encoder and Decoder Enable bit(1) 1 = IrDA encoder and decoder enabled 0 = IrDA encoder and decoder disabled RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin in Simplex mode 0 = UxRTS pin in Flow Control mode Unimplemented: Read as `0' UEN<1:0>: UARTx Enable bits 11 =UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches 10 =UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 =UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches 00 =UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by port latches WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit 1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = No wake-up enabled LPBACK: UARTx Loopback Mode Select bit 1 = Enable Loopback mode 0 = Loopback mode is disabled ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character - requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed URXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is `0' 0 = UxRX Idle state is `1' This feature is only available for the 16x BRG mode (BRGH = 0). Bit availability depends on pin availability. bit 14 bit 13 bit 12 bit 11 bit 10 bit 9-8 bit 7 bit 6 bit 5 bit 4 Note 1: 2: DS70165E-page 226 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 19-1: bit 3 UxMODE: UARTx MODE REGISTER (CONTINUED) BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit This feature is only available for the 16x BRG mode (BRGH = 0). Bit availability depends on pin availability. bit 2-1 bit 0 Note 1: 2: (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 227 dsPIC33F REGISTER 19-2: R/W-0 UTXISEL1 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15,13 HC = Hardware cleared W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 ADDEN R-1 RIDLE R-0 PERR R-0 FERR R/C-0 OERR R-0 URXDA bit 0 UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 UTXISEL0 U-0 -- R/W-0 HC UTXBRK R/W-0 UTXEN R-0 UTXBF R-1 TRMT bit 8 UTXINV(1) URXISEL<1:0> UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 =Reserved; do not use 10 =Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the transmit buffer becomes empty 01 =Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 =Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) UTXINV: IrDA Encoder Transmit Polarity Inversion bit(1) 1 = IrDA encoded, UxTX Idle state is `1' 0 = IrDA encoded, UxTX Idle state is `0' Unimplemented: Read as `0' UTXBRK: Transmit Break bit 1 = Send Sync Break on next transmission - Start bit, followed by twelve `0' bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission disabled or completed UTXEN: Transmit Enable bit 1 = Transmit enabled, UxTX pin controlled by UARTx 0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled by port. UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued URXISEL<1:0>: Receive Interrupt Mode Selection bits 11 =Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters) 10 =Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters) 0x =Interrupt is set when any character is received and transferred from the UxRSR to the receive buffer. Receive buffer has one or more characters. ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect. 0 = Address Detect mode disabled Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). bit 14 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7-6 bit 5 Note 1: DS70165E-page 228 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 19-2: bit 4 UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected OERR: Receive Buffer Overrun Error Status bit (read/clear only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed. Clearing a previously set OERR bit (1 0 transition) will reset the receiver buffer and the UxRSR to the empty state. URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). bit 3 bit 2 bit 1 bit 0 Note 1: (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 229 dsPIC33F NOTES: DS70165E-page 230 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 20.0 Note: ENHANCED CAN MODULE This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). messages on the CAN bus. Messages are transmitted by first loading the appropriate data registers. Status and errors can be checked by reading the appropriate registers. Any message detected on the CAN bus is checked for errors and then matched against filters to see if it should be received and stored in one of the receive registers. 20.2 20.1 Overview The Enhanced Controller Area Network (ECANTM) module is a serial interface, useful for communicating with other CAN modules or microcontroller devices. This interface/protocol was designed to allow communications within noisy environments. The dsPIC33F devices contain up to two ECAN modules. The CAN module is a communication controller implementing the CAN 2.0 A/B protocol, as defined in the BOSCH specification. The module will support CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B Active versions of the protocol. The module implementation is a full CAN system. The CAN specification is not covered within this data sheet. The reader may refer to the BOSCH CAN specification for further details. The module features are as follows: * Implementation of the CAN protocol, CAN 1.2, CAN 2.0A and CAN 2.0B * Standard and extended data frames * 0-8 bytes data length * Programmable bit rate up to 1 Mbit/sec * Automatic response to remote transmission requests * Up to 8 transmit buffers with application specified prioritization and abort capability (each buffer may contain up to 8 bytes of data) * Up to 32 receive buffers (each buffer may contain up to 8 bytes of data) * Up to 16 full (standard/extended identifier) acceptance filters * 3 full acceptance filter masks * DeviceNetTM addressing support * Programmable wake-up functionality with integrated low-pass filter * Programmable Loopback mode supports self-test operation * Signaling via interrupt capabilities for all CAN receiver and transmitter error states * Programmable clock source * Programmable link to input capture module (IC2 for both CAN1 and CAN2) for time-stamping and network synchronization * Low-power Sleep and Idle mode The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine handles all functions for receiving and transmitting (c) 2007 Microchip Technology Inc. Frame Types The CAN module transmits various types of frames which include data messages, or remote transmission requests initiated by the user, as other frames that are automatically generated for control purposes. The following frame types are supported: * Standard Data Frame: A standard data frame is generated by a node when the node wishes to transmit data. It includes an 11-bit Standard Identifier (SID), but not an 18-bit Extended Identifier (EID). * Extended Data Frame: An extended data frame is similar to a standard data frame, but includes an extended identifier as well. * Remote Frame: It is possible for a destination node to request the data from the source. For this purpose, the destination node sends a remote frame with an identifier that matches the identifier of the required data frame. The appropriate data source node will then send a data frame as a response to this remote request. * Error Frame: An error frame is generated by any node that detects a bus error. An error frame consists of two fields: an error flag field and an error delimiter field. * Overload Frame: An overload frame can be generated by a node as a result of two conditions. First, the node detects a dominant bit during interframe space which is an illegal condition. Second, due to internal conditions, the node is not yet able to start reception of the next message. A node may generate a maximum of 2 sequential overload frames to delay the start of the next message. * Interframe Space: Interframe space separates a proceeding frame (of whatever type) from a following data or remote frame. Preliminary DS70165E-page 231 dsPIC33F FIGURE 20-1: ECANTM MODULE BLOCK DIAGRAM RXF15 Filter RXF14 Filter RXF13 Filter RXF12 Filter DMA Controller RXF11 Filter RXF10 Filter RXF9 Filter RXF8 Filter TRB7 TX/RX Buffer Control Register TRB6 TX/RX Buffer Control Register TRB5 TX/RX Buffer Control Register TRB4 TX/RX Buffer Control Register TRB3 TX/RX Buffer Control Register TRB2 TX/RX Buffer Control Register TRB1 TX/RX Buffer Control Register TRB0 TX/RX Buffer Control Register RXF7 Filter RXF6 Filter RXF5 Filter RXF4 Filter RXF3 Filter RXF2 Filter RXF1 Filter RXF0 Filter RXM2 Mask RXM1 Mask RXM0 Mask Transmit Byte Sequencer Message Assembly Buffer Control Configuration Logic CAN Protocol Engine CPU Bus Interrupts CiTX(1) CiRX(1) Note 1: i = 1 or 2 refers to a particular ECAN module (ECAN1 or ECAN2). DS70165E-page 232 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 20.3 Modes of Operation Note: The CAN module can operate in one of several operation modes selected by the user. These modes include: * * * * * * Initialization Mode Disable Mode Normal Operation Mode Listen Only Mode Listen All Messages Mode Loopback Mode Typically, if the CAN module is allowed to transmit in a particular mode of operation and a transmission is requested immediately after the CAN module has been placed in that mode of operation, the module waits for 11 consecutive recessive bits on the bus before starting transmission. If the user switches to Disable mode within this 11-bit period, then this transmission is aborted and the corresponding TXABT bit is set and TXREQ bit is cleared. Modes are requested by setting the REQOP<2:0> bits (CiCTRL1<10:8>). Entry into a mode is Acknowledged by monitoring the OPMODE<2:0> bits (CiCTRL1<7:5>). The module will not change the mode and the OPMODE bits until a change in mode is acceptable, generally during bus Idle time, which is defined as at least 11 consecutive recessive bits. 20.3.3 NORMAL OPERATION MODE Normal Operation mode is selected when REQOP<2:0> = 000. In this mode, the module is activated and the I/O pins will assume the CAN bus functions. The module will transmit and receive CAN bus messages via the CiTX and CiRX pins. 20.3.1 INITIALIZATION MODE 20.3.4 LISTEN ONLY MODE In the Initialization mode, the module will not transmit or receive. The error counters are cleared and the interrupt flags remain unchanged. The programmer will have access to Configuration registers that are access restricted in other modes. The module will protect the user from accidentally violating the CAN protocol through programming errors. All registers which control the configuration of the module can not be modified while the module is on-line. The CAN module will not be allowed to enter the Configuration mode while a transmission is taking place. The Configuration mode serves as a lock to protect the following registers: * * * * * All Module Control Registers Baud Rate and Interrupt Configuration Registers Bus Timing Registers Identifier Acceptance Filter Registers Identifier Acceptance Mask Registers If the Listen Only mode is activated, the module on the CAN bus is passive. The transmitter buffers revert to the port I/O function. The receive pins remain inputs. For the receiver, no error flags or Acknowledge signals are sent. The error counters are deactivated in this state. The Listen Only mode can be used for detecting the baud rate on the CAN bus. To use this, it is necessary that there are at least two further nodes that communicate with each other. 20.3.5 LISTEN ALL MESSAGES MODE The module can be set to ignore all errors and receive any message. The Listen All Messages mode is activated by setting REQOP<2:0> = `111'. In this mode, the data which is in the message assembly buffer, until the time an error occurred, is copied in the receive buffer and can be read via the CPU interface. 20.3.2 DISABLE MODE 20.3.6 LOOPBACK MODE In Disable mode, the module will not transmit or receive. The module has the ability to set the WAKIF bit due to bus activity, however, any pending interrupts will remain and the error counters will retain their value. If the REQOP<2:0> bits (CiCTRL1<10:8>) = 001, the module will enter the Module Disable mode. If the module is active, the module will wait for 11 recessive bits on the CAN bus, detect that condition as an Idle bus, then accept the module disable command. When the OPMODE<2:0> bits (CiCTRL1<7:5>) = 001, that indicates whether the module successfully went into Module Disable mode. The I/O pins will revert to normal I/O function when the module is in the Module Disable mode. The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2<14>) enables or disables the filter. If the Loopback mode is activated, the module will connect the internal transmit signal to the internal receive signal at the module boundary. The transmit and receive pins revert to their port I/O function. 20.4 20.4.1 Message Reception RECEIVE BUFFERS The CAN bus module has up to 32 receive buffers, located in DMA RAM. The first 8 buffers need to be configured as receive buffers by clearing the corresponding TX/RX buffer selection (TXENn) bit in a CiTRmnCON register. The overall size of the CAN buffer area in DMA RAM is selectable by the user and is defined by the DMABS<2:0> bits (CiFCTRL<15:13>). The first 16 buffers can be assigned to receive filters, while the rest can be used only as a FIFO buffer. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 233 dsPIC33F An additional buffer is always committed to monitoring the bus for incoming messages. This buffer is called the Message Assembly Buffer (MAB). All messages are assembled by the MAB and are transferred to the buffers only if the acceptance filter criterion are met. When a message is received, the RBIF flag (CiINTF<1>) will be set. The user would then need to inspect the CiVEC and/or CiRXFUL1 register to determine which filter and buffer caused the interrupt to get generated. The RBIF bit can only be set by the module when a message is received. The bit is cleared by the user when it has completed processing the message in the buffer. If the RBIE bit is set, an interrupt will be generated when a message is received. 20.4.5 RECEIVE ERRORS The CAN module will detect the following receive errors: * Cyclic Redundancy Check (CRC) Error * Bit Stuffing Error * Invalid Message Receive Error These receive errors do not generate an interrupt. However, the receive error counter is incremented by one in case one of these errors occur. The RXWAR bit (CiINTF<9>) indicates that the receive error counter has reached the CPU warning limit of 96 and an interrupt is generated. 20.4.2 FIFO BUFFER MODE 20.4.6 RECEIVE INTERRUPTS The ECAN module provides FIFO buffer functionality if the buffer pointer for a filter has a value of `1111'. In this mode, the results of a hit on that buffer will write to the next available buffer location within the FIFO. The CiFCTRL register defines the size of the FIFO. The FSA<4:0> bits in this register define the start of the FIFO buffers. The end of the FIFO is defined by the DMABS<2:0> bits if DMA is enabled. Thus, FIFO sizes up to 32 buffers are supported. Receive interrupts can be divided into 3 major groups, each including various conditions that generate interrupts: * Receive Interrupt: A message has been successfully received and loaded into one of the receive buffers. This interrupt is activated immediately after receiving the End-of-Frame (EOF) field. Reading the RXnIF flag will indicate which receive buffer caused the interrupt. * Wake-up Interrupt: The CAN module has woken up from Disable mode or the device has woken up from Sleep mode. * Receive Error Interrupts: A receive error interrupt will be indicated by the ERRIF bit. This bit shows that an error condition occurred. The source of the error can be determined by checking the bits in the CAN Interrupt Flag register, CiINTF. - Invalid Message Received: If any type of error occurred during reception of the last message, an error will be indicated by the IVRIF bit. - Receiver Overrun: The RBOVIF bit (CiINTF<2>) indicates that an overrun condition occurred. - Receiver Warning: The RXWAR bit indicates that the receive error counter (RERRCNT<7:0>) has reached the warning limit of 96. - Receiver Error Passive: The RXEP bit indicates that the receive error counter has exceeded the error passive limit of 127 and the module has gone into error passive state. 20.4.3 MESSAGE ACCEPTANCE FILTERS The message acceptance filters and masks are used to determine if a message in the message assembly buffer should be loaded into either of the receive buffers. Once a valid message has been received into the Message Assembly Buffer (MAB), the identifier fields of the message are compared to the filter values. If there is a match, that message will be loaded into the appropriate receive buffer. Each filter is associated with a buffer pointer (FnBP<3:0>), which is used to link the filter to one of 16 receive buffers. The acceptance filter looks at incoming messages for the IDE bit (CiTRBnSID<0>) to determine how to compare the identifiers. If the IDE bit is clear, the message is a standard frame and only filters with the EXIDE bit (CiRXFnSID<3>) clear are compared. If the IDE bit is set, the message is an extended frame, and only filters with the EXIDE bit set are compared. 20.4.4 MESSAGE ACCEPTANCE FILTER MASKS The mask bits essentially determine which bits to apply the filter to. If any mask bit is set to a zero, then that bit will automatically be accepted regardless of the filter bit. There are three programmable acceptance filter masks associated with the receive buffers. Any of these three masks can be linked to each filter by selecting the desired mask in the FnMSK<1:0> bits in the appropriate CiFMSKSELn register. DS70165E-page 234 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 20.5 20.5.1 Message Transmission TRANSMIT BUFFERS 20.5.4 AUTOMATIC PROCESSING OF REMOTE TRANSMISSION REQUESTS The CAN module has up to eight transmit buffers, located in DMA RAM. These 8 buffers need to be configured as transmit buffers by setting the corresponding TX/RX buffer selection (TXENn or TXENm) bit in a CiTRmnCON register. The overall size of the CAN buffer area in DMA RAM is selectable by the user and is defined by the DMABS<2:0> bits (CiFCTRL<15:13>). Each transmit buffer occupies 16 bytes of data. Eight of the bytes are the maximum 8 bytes of the transmitted message. Five bytes hold the standard and extended identifiers and other message arbitration information. The last byte is unused. If the RTRENn bit (in the CiTRmnCON register) for a particular transmit buffer is set, the hardware automatically transmits the data in that buffer in response to remote transmission requests matching the filter that points to that particular buffer. The user does not need to manually initiate a transmission in this case. 20.5.5 ABORTING MESSAGE TRANSMISSION 20.5.2 TRANSMIT MESSAGE PRIORITY Transmit priority is a prioritization within each node of the pending transmittable messages. There are four levels of transmit priority. If the TXnPRI<1:0> bits (in CiTRmnCON) for a particular message buffer are set to `11', that buffer has the highest priority. If the TXnPRI<1:0> bits for a particular message buffer are set to `10' or `01', that buffer has an intermediate priority. If the TXnPRI<1:0> bits for a particular message buffer are `00', that buffer has the lowest priority. If two or more pending messages have the same priority, the messages are transmitted in decreasing order of buffer index. The system can also abort a message by clearing the TXREQ bit associated with each message buffer. Setting the ABAT bit (CiCTRL1<12>) will request an abort of all pending messages. If the message has not yet started transmission, or if the message started but is interrupted by loss of arbitration or an error, the abort will be processed. The abort is indicated when the module sets the TXABT bit and the TXnIF flag is not automatically set. 20.5.6 TRANSMISSION ERRORS The CAN module will detect the following transmission errors: * Acknowledge Error * Form Error * Bit Error These transmission errors will not necessarily generate an interrupt but are indicated by the transmission error counter. However, each of these errors will cause the transmission error counter to be incremented by one. Once the value of the error counter exceeds the value of 96, the ERRIF (CiINTF<5>) and the TXWAR bit (CiINTF<10>) are set. Once the value of the error counter exceeds the value of 96, an interrupt is generated and the TXWAR bit in the Interrupt Flag register is set. 20.5.3 TRANSMISSION SEQUENCE To initiate transmission of the message, the TXREQn bit (in CiTRmnCON) must be set. The CAN bus module resolves any timing conflicts between the setting of the TXREQn bit and the Start-of-Frame (SOF), ensuring that if the priority was changed, it is resolved correctly before the SOF occurs. When TXREQn is set, the TXABTn, TXLARBn and TXERRn flag bits are automatically cleared. Setting the TXREQn bit simply flags a message buffer as enqueued for transmission. When the module detects an available bus, it begins transmitting the message which has been determined to have the highest priority. If the transmission completes successfully on the first attempt, the TXREQn bit is cleared automatically and an interrupt is generated if TXnIE was set. If the message transmission fails, one of the error condition flags will be set and the TXREQn bit will remain set, indicating that the message is still pending for transmission. If the message encountered an error condition during the transmission attempt, the TXERRn bit will be set and the error condition may cause an interrupt. If the message loses arbitration during the transmission attempt, the TXLARBn bit is set. No interrupt is generated to signal the loss of arbitration. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 235 dsPIC33F 20.5.7 TRANSMIT INTERRUPTS 20.6 Baud Rate Setting Transmit interrupts can be divided into 2 major groups, each including various conditions that generate interrupts: * Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. Reading the TXnIF flags will indicate which transmit buffer is available and caused the interrupt. * Transmit Error Interrupts: A transmission error interrupt will be indicated by the ERRIF flag. This flag shows that an error condition occurred. The source of the error can be determined by checking the error flags in the CAN Interrupt Flag register, CiINTF. The flags in this register are related to receive and transmit errors. - Transmitter Warning Interrupt: The TXWAR bit indicates that the transmit error counter has reached the CPU warning limit of 96. - Transmitter Error Passive: The TXEP bit (CiINTF<12>) indicates that the transmit error counter has exceeded the error passive limit of 127 and the module has gone to error passive state. - Bus Off: The TXBO bit (CiINTF<13>) indicates that the transmit error counter has exceeded 255 and the module has gone to the bus off state. Note: Both ECAN1 and ECAN2 can trigger a DMA data transfer. If C1TX, C1RX, C2TX or C2RX is selected as a DMA IRQ source, a DMA transfer occurs when the C1TXIF, C1RXIF, C2TXIF or C2RXIF bit gets set as a result of an ECAN1 or ECAN2 transmission or reception. All nodes on any particular CAN bus must have the same nominal bit rate. In order to set the baud rate, the following parameters have to be initialized: * * * * * * Synchronization Jump Width Baud Rate Prescaler Phase Segments Length Determination of Phase Segment 2 Sample Point Propagation Segment bits 20.6.1 BIT TIMING All controllers on the CAN bus must have the same baud rate and bit length. However, different controllers are not required to have the same master oscillator clock. At different clock frequencies of the individual controllers, the baud rate has to be adjusted by adjusting the number of time quanta in each segment. The nominal bit time can be thought of as being divided into separate non-overlapping time segments. These segments are shown in Figure 20-2. * * * * Synchronization Segment (Sync Seg) Propagation Time Segment (Prop Seg) Phase Segment 1 (Phase1 Seg) Phase Segment 2 (Phase2 Seg) The time segments and also the nominal bit time are made up of integer units of time called time quanta or TQ. By definition, the nominal bit time has a minimum of 8 TQ and a maximum of 25 TQ. Also, by definition, the minimum nominal bit time is 1 sec corresponding to a maximum bit rate of 1 MHz. FIGURE 20-2: Input Signal ECANTM MODULE BIT TIMING Sync Prop Segment Phase Segment 1 Sample Point Phase Segment 2 Sync TQ DS70165E-page 236 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 20.6.2 PRESCALER SETTING There is a programmable prescaler with integral values ranging from 1 to 64, in addition to a fixed divide-by-2 for clock generation. The time quantum (TQ) is a fixed unit of time derived from the oscillator period and is given by Equation 20-1. Note: FCAN must not exceed 40 MHz. If CANCKS = 0, then FCY must not exceed 20 MHz. Typically, the sampling of the bit should take place at about 60-70% through the bit time, depending on the system parameters. 20.6.6 SYNCHRONIZATION EQUATION 20-1: TIME QUANTUM FOR CLOCK GENERATION To compensate for phase shifts between the oscillator frequencies of the different bus stations, each CAN controller must be able to synchronize to the relevant signal edge of the incoming signal. When an edge in the transmitted data is detected, the logic will compare the location of the edge to the expected time (Synchronous Segment). The circuit will then adjust the values of Phase1 Seg and Phase2 Seg. There are two mechanisms used to synchronize. TQ = 2 (BRP<5:0> + 1)/FCAN 20.6.6.1 20.6.3 PROPAGATION SEGMENT Hard Synchronization This part of the bit time is used to compensate physical delay times within the network. These delay times consist of the signal propagation time on the bus line and the internal delay time of the nodes. The Prop Seg can be programmed from 1 TQ to 8 TQ by setting the PRSEG<2:0> bits (CiCFG2<2:0>). Hard synchronization is only done whenever there is a `recessive' to `dominant' edge during bus Idle, indicating the start of a message. After hard synchronization, the bit time counters are restarted with the Sync Seg. Hard synchronization forces the edge which has caused the hard synchronization to lie within the synchronization segment of the restarted bit time. If a hard synchronization is done, there will not be a resynchronization within that bit time. 20.6.4 PHASE SEGMENTS 20.6.6.2 Resynchronization As a result of resynchronization, Phase1 Seg may be lengthened or Phase2 Seg may be shortened. The amount of lengthening or shortening of the phase buffer segment has an upper boundary known as the synchronization jump width, and is specified by the SJW<1:0> bits (CiCFG1<7:6>). The value of the synchronization jump width will be added to Phase1 Seg or subtracted from Phase2 Seg. The resynchronization jump width is programmable between 1 TQ and 4 TQ. The following requirement must be fulfilled while setting the SJW<1:0> bits: Phase2 Seg > Synchronization Jump Width Note: In the register descriptions that follow, `i' in the register identifier denotes the specific ECAN module (ECAN1 or ECAN2). `n' in the register identifier denotes the buffer, filter or mask number. `m' in the register identifier denotes the word number within a particular CAN data field. The phase segments are used to optimally locate the sampling of the received bit within the transmitted bit time. The sampling point is between Phase1 Seg and Phase2 Seg. These segments are lengthened or shortened by resynchronization. The end of the Phase1 Seg determines the sampling point within a bit period. The segment is programmable from 1 TQ to 8 TQ. Phase2 Seg provides delay to the next transmitted data transition. The segment is programmable from 1 TQ to 8 TQ, or it may be defined to be equal to the greater of Phase1 Seg or the information processing time (2 TQ). The Phase1 Seg is initialized by setting bits SEG1PH<2:0> (CiCFG2<5:3>) and Phase2 Seg is initialized by setting SEG2PH<2:0> (CiCFG2<10:8>). The following requirement must be fulfilled while setting the lengths of the phase segments: Prop Seg + Phase1 Seg Phase2 Seg 20.6.5 SAMPLE POINT The sample point is the point of time at which the bus level is read and interpreted as the value of that respective bit. The location is at the end of Phase1 Seg. If the bit timing is slow and contains many TQ, it is possible to specify multiple sampling of the bus line at the sample point. The level determined by the CAN bus then corresponds to the result from the majority decision of three values. The majority samples are taken at the sample point and twice before with a distance of TQ/2. The CAN module allows the user to choose between sampling three times at the same point or once at the same point, by setting or clearing the SAM bit (CiCFG2<6>). (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 237 dsPIC33F REGISTER 20-1: U-0 -- bit 15 R-1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 OPMODE<2:0> R-0 U-0 -- R/W-0 CANCAP U-0 -- U-0 -- CiCTRL1: ECAN CONTROL REGISTER 1 U-0 -- R/W-0 CSIDL R/W-0 ABAT R/W-0 CANCKS R/W-1 R/W-0 REQOP<2:0> bit 8 R/W-0 WIN bit 0 R/W-0 Unimplemented: Read as `0' CSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode ABAT: Abort All Pending Transmissions bit Signal all transmit buffers to abort transmission. Module will clear this bit when all transmissions are aborted CANCKS: CAN Master Clock Select bit 1 = CAN FCAN clock is FCY 0 = CAN FCAN clock is FOSC REQOP<2:0>: Request Operation Mode bits 000 = Set Normal Operation mode 001 = Set Disable mode 010 = Set Loopback mode 011 = Set Listen Only Mode 100 = Set Configuration mode 101 = Reserved - do not use 110 = Reserved - do not use 111 = Set Listen All Messages mode OPMODE<2:0>: Operation Mode bits 000 = Module is in Normal Operation mode 001 = Module is in Disable mode 010 = Module is in Loopback mode 011 = Module is in Listen Only mode 100 = Module is in Configuration mode 101 = Reserved 110 = Reserved 111 = Module is in Listen All Messages mode Unimplemented: Read as `0' CANCAP: CAN Message Receive Timer Capture Event Enable bit 1 = Enable input capture based on CAN message receive 0 = Disable CAN capture Unimplemented: Read as `0' WIN: SFR Map Window Select bit 1 = Use filter window 0 = Use buffer window bit 12 bit 11 bit 10-8 bit 7-5 bit 4 bit 3 bit 2-1 bit 0 DS70165E-page 238 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 20-2: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-5 bit 4-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R-0 R-0 R-0 DNCNT<4:0> bit 0 R-0 R-0 CiCTRL2: ECAN CONTROL REGISTER 2 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 Unimplemented: Read as `0' DNCNT<4:0>: DeviceNetTM Filter Bit Number bits 10010-11111 = Invalid selection 10001 = Compare up to data byte 3, bit 6 with EID<17> .... 00001 = Compare up to data byte 1, bit 7 with EID<0> 00000 = Do not compare data bytes (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 239 dsPIC33F REGISTER 20-3: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-1 R-0 R-0 R-0 ICODE<6:0> bit 0 R-0 R-0 R-0 CiVEC: ECAN INTERRUPT CODE REGISTER U-0 -- U-0 -- R-0 R-0 R-0 FILHIT<4:0> bit 8 R-0 R-0 Unimplemented: Read as `0' FILHIT<4:0>: Filter Hit Number bits 10000-11111 = Reserved 01111 = Filter 15 .... 00001 = Filter 1 00000 = Filter 0 Unimplemented: Read as `0' ICODE<6:0>: Interrupt Flag Code bits 1000101-1111111 = Reserved 1000100 = FIFO almost full interrupt 1000011 = Receiver overflow interrupt 1000010 = Wake-up interrupt 1000001 = Error interrupt 1000000 = No interrupt 0010000-0111111 = Reserved 0001111 = RB15 buffer Interrupt .... 0001001 = RB9 buffer interrupt 0001000 = RB8 buffer interrupt 0000111 = TRB7 buffer interrupt 0000110 = TRB6 buffer interrupt 0000101 = TRB5 buffer interrupt 0000100 = TRB4 buffer interrupt 0000011 = TRB3 buffer interrupt 0000010 = TRB2 buffer interrupt 0000001 = TRB1 buffer interrupt 0000000 = TRB0 Buffer interrupt bit 7 bit 6-0 DS70165E-page 240 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 20-4: R/W-0 bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 FSA<4:0> bit 0 R/W-0 CiFCTRL: ECAN FIFO CONTROL REGISTER R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 DMABS<2:0> DMABS<2:0>: DMA Buffer Size bits 111 = Reserved 110 = 32 buffers in DMA RAM 101 = 24 buffers in DMA RAM 100 = 16 buffers in DMA RAM 011 = 12 buffers in DMA RAM 010 = 8 buffers in DMA RAM 001 = 6 buffers in DMA RAM 000 = 4 buffers in DMA RAM Unimplemented: Read as `0' FSA<4:0>: FIFO Area Starts with Buffer bits 11111 = RB31 buffer 11110 = RB30 buffer .... 00001 = TRB1 buffer 00000 = TRB0 buffer bit 12-5 bit 4-0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 241 dsPIC33F REGISTER 20-5: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R-0 R-0 R-0 R-0 FNRB<5:0> bit 0 R-0 R-0 CiFIFO: ECAN FIFO STATUS REGISTER U-0 -- R-0 R-0 R-0 R-0 FBP<5:0> bit 8 R-0 R-0 Unimplemented: Read as `0' FBP<5:0>: FIFO Write Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer .... 000001 = TRB1 buffer 000000 = TRB0 buffer Unimplemented: Read as `0' FNRB<5:0>: FIFO Next Read Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer .... 000001 = TRB1 buffer 000000 = TRB0 buffer bit 7-6 bit 5-0 DS70165E-page 242 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 20-6: U-0 -- bit 15 R/C-0 IVRIF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/C-0 WAKIF R/C-0 ERRIF U-0 -- R/C-0 FIFOIF R/C-0 RBOVIF R/C-0 RBIF CiINTF: ECAN INTERRUPT FLAG REGISTER U-0 -- R-0 TXBO R-0 TXBP R-0 RXBP R-0 TXWAR R-0 RXWAR R-0 EWARN bit 8 R/C-0 TBIF bit 0 Unimplemented: Read as `0' TXBO: Transmitter in Error State Bus Off bit TXBP: Transmitter in Error State Bus Passive bit RXBP: Receiver in Error State Bus Passive bit TXWAR: Transmitter in Error State Warning bit RXWAR: Receiver in Error State Warning bit EWARN: Transmitter or Receiver in Error State Warning bit IVRIF: Invalid Message Received Interrupt Flag bit WAKIF: Bus Wake-up Activity Interrupt Flag bit ERRIF: Error Interrupt Flag bit (multiple sources in CiINTF<13:8> register) Unimplemented: Read as `0' FIFOIF: FIFO Almost Full Interrupt Flag bit RBOVIF: RX Buffer Overflow Interrupt Flag bit RBIF: RX Buffer Interrupt Flag bit TBIF: TX Buffer Interrupt Flag bit (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 243 dsPIC33F REGISTER 20-7: U-0 -- bit 15 R/W-0 IVRIE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 WAKIE R/W-0 ERRIE R/W-0 -- R/W-0 FIFOIE R/W-0 RBOVIE R/W-0 RBIE CiINTE: ECAN INTERRUPT ENABLE REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 TBIE bit 0 Unimplemented: Read as `0' IVRIE: Invalid Message Received Interrupt Enable bit WAKIE: Bus Wake-up Activity Interrupt Flag bit ERRIE: Error Interrupt Enable bit Unimplemented: Read as `0' FIFOIE: FIFO Almost Full Interrupt Enable bit RBOVIE: RX Buffer Overflow Interrupt Enable bit RBIE: RX Buffer Interrupt Enable bit TBIE: TX Buffer Interrupt Enable bit DS70165E-page 244 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 20-8: R-0 bit 15 R-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 0 CiEC: ECAN TRANSMIT/RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 8 TERRCNT<7:0> RERRCNT<7:0> TERRCNT<7:0>: Transmit Error Count bits RERRCNT<7:0>: Receive Error Count bits (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 245 dsPIC33F REGISTER 20-9: U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CiCFG1: ECAN BAUD RATE CONFIGURATION REGISTER 1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 bit 0 SJW<1:0> BRP<5:0> Unimplemented: Read as `0' SJW<1:0>: Synchronization Jump Width bits 11 = Length is 4 x TQ 10 = Length is 3 x TQ 01 = Length is 2 x TQ 00 = Length is 1 x TQ BRP<5:0>: Baud Rate Prescaler bits 11 1111 = TQ = 2 x 64 x 1/FCAN 00 0010 = TA = 2 x 3 x 1/FCAN 00 0001 = TA = 2 x 2 x 1/FCAN 00 0000 = TQ = 2 x 1 x 1/FCAN bit 5-0 DS70165E-page 246 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 20-10: CiCFG2: ECAN BAUD RATE CONFIGURATION REGISTER 2 U-0 -- bit 15 R/W-x SEG2PHTS bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x SAM R/W-x R/W-x SEG1PH<2:0> R/W-x R/W-x R/W-x PRSEG<2:0> bit 0 R/W-x WAKFIL U-0 -- U-0 -- U-0 -- R/W-x R/W-x SEG2PH<2:0> bit 8 R/W-x R/W-x Unimplemented: Read as `0' WAKFIL: Select CAN bus Line Filter for Wake-up bit 1 = Use CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up Unimplemented: Read as `0' SEG2PH<2:0>: Phase Buffer Segment 2 bits 111 = Length is 8 x TQ 000 = Length is 1 x TQ SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of SEG1PH bits or Information Processing Time (IPT), whichever is greater SAM: Sample of the CAN bus Line bit 1 = Bus line is sampled three times at the sample point 0 = Bus line is sampled once at the sample point SEG1PH<2:0>: Phase Buffer Segment 1 bits 111 = Length is 8 x TQ 000 = Length is 1 x TQ PRSEG<2:0>: Propagation Time Segment bits 111 = Length is 8 x TQ 000 = Length is 1 x TQ bit 13-11 bit 10-8 bit 7 bit 6 bit 5-3 bit 2-0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 247 dsPIC33F REGISTER 20-11: CiFEN1: ECAN ACCEPTANCE FILTER ENABLE REGISTER R/W-0 FLTEN15 bit 15 R/W-0 FLTEN7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 FLTEN6 R/W-1 FLTEN5 R/W-1 FLTEN4 R/W-1 FLTEN3 R/W-1 FLTEN2 R/W-1 FLTEN1 R/W-0 FLTEN14 R/W-0 FLTEN13 R/W-0 FLTEN12 R/W-0 FLTEN11 R/W-0 FLTEN10 R/W-0 FLTEN9 R/W-0 FLTEN8 bit 8 R/W-1 FLTEN0 bit 0 FLTENn: Enable Filter n to Accept Messages bits 1 = Enable Filter n 0 = Disable Filter n REGISTER 20-12: CiBUFPNT1: ECAN FILTER 0-3 BUFFER POINTER REGISTER R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-8 bit 7-4 bit 3-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 F3BP<3:0> F2BP<3:0> F1BP<3:0> F0BP<3:0> F3BP<3:0>: RX Buffer Written when Filter 3 Hits bits F2BP<3:0>: RX Buffer Written when Filter 2 Hits bits F1BP<3:0>: RX Buffer Written when Filter 1 Hits bits F0BP<3:0>: RX Buffer Written when Filter 0 Hits bits 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 .... 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 DS70165E-page 248 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 20-13: CiBUFPNT2: ECAN FILTER 4-7 BUFFER POINTER REGISTER R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-8 bit 7-4 bit 3-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 F7BP<3:0> F6BP<3:0> F5BP<3:0> F4BP<3:0> F7BP<3:0>: RX Buffer Written when Filter 7 Hits bits F6BP<3:0>: RX Buffer Written when Filter 6 Hits bits F5BP<3:0>: RX Buffer Written when Filter 5 Hits bits F4BP<3:0>: RX Buffer Written when Filter 4 Hits bits REGISTER 20-14: CiBUFPNT3: ECAN FILTER 8-11 BUFFER POINTER REGISTER R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-8 bit 7-4 bit 3-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 F11BP<3:0> F10BP<3:0> F9BP<3:0> F8BP<3:0> F11BP<3:0>: RX Buffer Written when Filter 11 Hits bits F10BP<3:0>: RX Buffer Written when Filter 10 Hits bits F9BP<3:0>: RX Buffer Written when Filter 9 Hits bits F8BP<3:0>: RX Buffer Written when Filter 8 Hits bits (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 249 dsPIC33F REGISTER 20-15: CiBUFPNT4: ECAN FILTER 12-15 BUFFER POINTER REGISTER R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-8 bit 7-4 bit 3-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 F15BP<3:0> F14BP<3:0> F13BP<3:0> F12BP<3:0> F15BP<3:0>: RX Buffer Written when Filter 15 Hits bits F14BP<3:0>: RX Buffer Written when Filter 14 Hits bits F13BP<3:0>: RX Buffer Written when Filter 13 Hits bits F12BP<3:0>: RX Buffer Written when Filter 12 Hits bits DS70165E-page 250 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 20-16: R/W-x SID10 bit 15 R/W-x SID2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x SID1 R/W-x SID0 U-0 -- R/W-x EXIDE U-0 -- R/W-x EID17 CiRXFnSID: ECAN ACCEPTANCE FILTER n STANDARD IDENTIFIER (n = 0, 1, ..., 15) R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3 bit 8 R/W-x EID16 bit 0 SID<10:0>: Standard Identifier bits 1 = Message address bit SIDx must be `1' to match filter 0 = Message address bit SIDx must be `0' to match filter Unimplemented: Read as `0' EXIDE: Extended Identifier Enable bit If MIDE = 1 then: 1 = Match only messages with extended identifier addresses 0 = Match only messages with standard identifier addresses If MIDE = 0 then: Ignore EXIDE bit. Unimplemented: Read as `0' EID<17:16>: Extended Identifier bits 1 = Message address bit EIDx must be `1' to match filter 0 = Message address bit EIDx must be `0' to match filter bit 4 bit 3 bit 2 bit 1-0 REGISTER 20-17: R/W-x EID15 bit 15 R/W-x EID7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 CiRXFnEID: ECAN ACCEPTANCE FILTER n EXTENDED IDENTIFIER (n = 0, 1, ..., 15) R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 8 R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown EID<15:0>: Extended Identifier bits 1 = Message address bit EIDx must be `1' to match filter 0 = Message address bit EIDx must be `0' to match filter (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 251 dsPIC33F REGISTER 20-18: CiFMSKSEL1: ECAN FILTER 7-0 MASK SELECTION REGISTER R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-12 bit 11-10 bit 9-8 bit 7-6 bit 5-4 bit 3-2 bit 1-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> F7MSK<1:0>: Mask Source for Filter 7 bit F6MSK<1:0>: Mask Source for Filter 6 bit F5MSK<1:0>: Mask Source for Filter 5 bit F4MSK<1:0>: Mask Source for Filter 4 bit F3MSK<1:0>: Mask Source for Filter 3 bit F2MSK<1:0>: Mask Source for Filter 2 bit F1MSK<1:0>: Mask Source for Filter 1 bit F0MSK<1:0>: Mask Source for Filter 0 bit 11 = No mask 10 = Acceptance Mask 2 registers contain mask 01 = Acceptance Mask 1 registers contain mask 00 = Acceptance Mask 0 registers contain mask DS70165E-page 252 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 20-19: CiRXMnSID: ECAN ACCEPTANCE FILTER MASK n STANDARD IDENTIFIER R/W-x SID10 bit 15 R/W-x SID2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x SID1 R/W-x SID0 U-0 -- R/W-x MIDE U-0 -- R/W-x EID17 R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3 bit 8 R/W-x EID16 bit 0 SID<10:0>: Standard Identifier bits 1 = Include bit SIDx in filter comparison 0 = Bit SIDx is don't care in filter comparison Unimplemented: Read as `0' MIDE: Identifier Receive Mode bit 1 = Match only message types (standard or extended address) that correspond to EXIDE bit in filter 0 = Match either standard or extended address message if filters match (i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID)) Unimplemented: Read as `0' EID<17:16>: Extended Identifier bits 1 = Include bit EIDx in filter comparison 0 = Bit EIDx is don't care in filter comparison bit 4 bit 3 bit 2 bit 1-0 REGISTER 20-20: CiRXMnEID: ECAN ACCEPTANCE FILTER MASK n EXTENDED IDENTIFIER R/W-x EID15 bit 15 R/W-x EID7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 8 R/W-x EID0 bit 0 EID<15:0>: Extended Identifier bits 1 = Include bit EIDx in filter comparison 0 = Bit EIDx is don't care in filter comparison (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 253 dsPIC33F REGISTER 20-21: CiRXFUL1: ECAN RECEIVE BUFFER FULL REGISTER 1 R/C-0 RXFUL15 bit 15 R/C-0 RXFUL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/C-0 RXFUL6 R/C-0 RXFUL5 R/C-0 RXFUL4 R/C-0 RXFUL3 R/C-0 RXFUL2 R/C-0 RXFUL1 R/C-0 RXFUL14 R/C-0 RXFUL13 R/C-0 RXFUL12 R/C-0 RXFUL11 R/C-0 RXFUL10 R/C-0 RXFUL9 R/C-0 RXFUL8 bit 8 R/C-0 RXFUL0 bit 0 RXFUL<15:0>: Receive Buffer n Full bits 1 = Buffer is full (set by module) 0 = Buffer is empty (clear by application software) REGISTER 20-22: CiRXFUL2: ECAN RECEIVE BUFFER FULL REGISTER 2 R/C-0 RXFUL31 bit 15 R/C-0 RXFUL23 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/C-0 RXFUL22 R/C-0 RXFUL21 R/C-0 RXFUL20 R/C-0 RXFUL19 R/C-0 RXFUL18 R/C-0 RXFUL17 R/C-0 RXFUL30 R/C-0 RXFUL29 R/C-0 RXFUL28 R/C-0 RXFUL27 R/C-0 RXFUL26 R/C-0 RXFUL25 R/C-0 RXFUL24 bit 8 R/C-0 RXFUL16 bit 0 RXFUL<31:16>: Receive Buffer n Full bits 1 = Buffer is full (set by module) 0 = Buffer is empty (clear by application software) DS70165E-page 254 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 20-23: CiRXOVF1: ECAN RECEIVE BUFFER OVERFLOW REGISTER 1 R/C-0 RXOVF15 bit 15 R/C-0 RXOVF7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/C-0 RXOVF6 R/C-0 RXOVF5 R/C-0 RXOVF4 R/C-0 RXOVF3 R/C-0 RXOVF2 R/C-0 RXOVF1 R/C-0 RXOVF14 R/C-0 RXOVF13 R/C-0 RXOVF12 R/C-0 RXOVF11 R/C-0 RXOVF10 R/C-0 RXOVF9 R/C-0 RXOVF8 bit 8 R/C-0 RXOVF0 bit 0 RXOVF<15:0>: Receive Buffer n Overflow bits 1 = Module pointed a write to a full buffer (set by module) 0 = Overflow is cleared (clear by application software) REGISTER 20-24: CiRXOVF2: ECAN RECEIVE BUFFER OVERFLOW REGISTER 2 R/C-0 RXOVF31 bit 15 R/C-0 RXOVF23 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/C-0 RXOVF22 R/C-0 RXOVF21 R/C-0 RXOVF20 R/C-0 RXOVF19 R/C-0 RXOVF18 R/C-0 RXOVF17 R/C-0 RXOVF30 R/C-0 RXOVF29 R/C-0 RXOVF28 R/C-0 RXOVF27 R/C-0 RXOVF26 R/C-0 RXOVF25 R/C-0 RXOVF24 bit 8 R/C-0 RXOVF16 bit 0 RXOVF<31:16>: Receive Buffer n Overflow bits 1 = Module pointed a write to a full buffer (set by module) 0 = Overflow is cleared (clear by application software) (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 255 dsPIC33F REGISTER 20-25: R/W-0 TXENn bit 15 R/W-0 TXENm bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 TXABTm(1) R-0 R-0 R/W-0 TXREQm R/W-0 RTRENm R/W-0 CiTRmnCON: ECAN TX/RX BUFFER m CONTROL REGISTER (m = 0,2,4,6; n = 1,3,5,7) R-0 R-0 TXLARBn R-0 TXERRn R/W-0 TXREQn R/W-0 RTRENn R/W-0 R/W-0 bit 8 R/W-0 bit 0 TXnPRI<1:0> TXABTn TXLARBm(1) TXERRm(1) TXmPRI<1:0> See Definition for Bits 7-0, Controls Buffer n TXENm: TX/RX Buffer Selection bit 1 = Buffer TRBn is a transmit buffer 0 = Buffer TRBn is a receive buffer TXABTm: Message Aborted bit(1) 1 = Message was aborted 0 = Message completed transmission successfully TXLARBm: Message Lost Arbitration bit(1) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent TXERRm: Error Detected During Transmission bit(1) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent TXREQm: Message Send Request bit Setting this bit to `1' requests sending a message. The bit will automatically clear when the message is successfully sent. Clearing the bit to `0' while set will request a message abort. RTRENm: Auto-Remote Transmit Enable bit 1 = When a remote transmit is received, TXREQ will be set 0 = When a remote transmit is received, TXREQ will be unaffected TXmPRI<1:0>: Message Transmission Priority bits 11 = Highest message priority 10 = High intermediate message priority 01 = Low intermediate message priority 00 = Lowest message priority This bit is cleared when TXREQ is set. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0 Note 1: DS70165E-page 256 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F Note: The buffers, SID, EID, DLC, Data Field and Receive Status registers are located in DMA RAM. REGISTER 20-26: CiTRBnSID: ECAN BUFFER n STANDARD IDENTIFIER (n = 0, 1, ..., 31) U-0 -- bit 15 R/W-x SID5 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-2 bit 1 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x SID4 R/W-x SID3 R/W-x SID2 R/W-x SID1 R/W-x SID0 R/W-x SRR U-0 -- U-0 -- R/W-x SID10 R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 bit 8 R/W-x IDE bit 0 Unimplemented: Read as `0' SID<10:0>: Standard Identifier bits SRR: Substitute Remote Request bit 1 = Message will request remote transmission 0 = Normal message IDE: Extended Identifier bit 1 = Message will transmit extended identifier 0 = Message will transmit standard identifier bit 0 REGISTER 20-27: CiTRBnEID: ECAN BUFFER n EXTENDED IDENTIFIER (n = 0, 1, ..., 31) U-0 -- bit 15 R/W-x EID13 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 R/W-x EID7 U-0 -- U-0 -- U-0 -- R/W-x EID17 R/W-x EID16 R/W-x EID15 R/W-x EID14 bit 8 R/W-x EID6 bit 0 Unimplemented: Read as `0' EID<17:6>: Extended Identifier bits (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 257 dsPIC33F REGISTER 20-28: CiTRBnDLC: ECAN BUFFER n DATA LENGTH CONTROL (n = 0, 1, ..., 31) R/W-x EID5 bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-x RB0 R/W-x DLC3 R/W-x DLC2 R/W-x DLC1 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 R/W-x RTR R/W-x RB1 bit 8 R/W-x DLC0 bit 0 EID<5:0>: Extended Identifier bits RTR: Remote Transmission Request bit 1 = Message will request remote transmission 0 = Normal message RB1: Reserved Bit 1 User must set this bit to `0' per CAN protocol. Unimplemented: Read as `0' RB0: Reserved Bit 0 User must set this bit to `0' per CAN protocol. DLC<3:0>: Data Length Code bits bit 8 bit 7-5 bit 4 bit 3-0 REGISTER 20-29: R/W-x TRBnDm7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 Note 1: CiTRBnDm: ECAN BUFFER n DATA FIELD BYTE m (n = 0, 1, ..., 31; m = 0, 1, ..., 7)(1) R/W-x TRBnDm5 R/W-x TRBnDm4 R/W-x TRBnDm3 R/W-x TRBnDm2 R/W-x TRBnDm1 R/W-x TRBnDm0 bit 0 R/W-x TRBnDm6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TRnDm<7:0>: Data Field Buffer `n' Byte `m' bits The Most Significant Byte contains byte (m + 1) of the buffer. DS70165E-page 258 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 20-30: CiTRBnSTAT: ECAN RECEIVE BUFFER n STATUS (n = 0, 1, ..., 31) U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 U-0 -- U-0 -- R/W-x FILHIT4 R/W-x FILHIT3 R/W-x FILHIT2 R/W-x FILHIT1 R/W-x FILHIT0 bit 8 Unimplemented: Read as `0' FILHIT<4:0>: Filter Hit Code bits (only written by module for receive buffers, unused for transmit buffers) Encodes number of filter that resulted in writing this buffer. Unimplemented: Read as `0' (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 259 dsPIC33F NOTES: DS70165E-page 260 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 21.0 Note: DATA CONVERTER INTERFACE (DCI) MODULE This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). 21.2.3 CSDI PIN The Serial Data Input (CSDI) pin is configured as an input only pin when the module is enabled. 21.2.3.1 COFS Pin 21.1 Module Introduction The Codec Frame Synchronization (COFS) pin is used to synchronize data transfers that occur on the CSDO and CSDI pins. The COFS pin may be configured as an input or an output. The data direction for the COFS pin is determined by the COFSD control bit in the DCICON1 register. The DCI module accesses the shadow registers while the CPU is in the process of accessing the memory mapped buffer registers. The dsPIC33F Data Converter Interface (DCI) module allows simple interfacing of devices, such as audio coder/decoders (Codecs), ADC and D/A converters. The following interfaces are supported: * Framed Synchronous Serial Transfer (Single or Multi-Channel) * Inter-IC Sound (I2S) Interface * AC-Link Compliant mode The DCI module provides the following general features: * Programmable word size up to 16 bits * Supports up to 16 time slots, for a maximum frame size of 256 bits * Data buffering for up to 4 samples without CPU overhead 21.2.4 BUFFER DATA ALIGNMENT Data values are always stored left justified in the buffers since most Codec data is represented as a signed 2's complement fractional number. If the received word length is less than 16 bits, the unused Least Significant bits in the Receive Buffer registers are set to `0' by the module. If the transmitted word length is less than 16 bits, the unused LSbs in the Transmit Buffer register are ignored by the module. The word length setup is described in subsequent sections of this document. 21.2.5 21.2 Module I/O Pins TRANSMIT/RECEIVE SHIFT REGISTER There are four I/O pins associated with the module. When enabled, the module controls the data direction of each of the four pins. The DCI module has a 16-bit shift register for shifting serial data in and out of the module. Data is shifted in/ out of the shift register, MSb first, since audio PCM data is transmitted in signed 2's complement format. 21.2.1 CSCK PIN 21.2.6 DCI BUFFER CONTROL The CSCK pin provides the serial clock for the DCI module. The CSCK pin may be configured as an input or output using the CSCKD control bit in the DCICON1 SFR. When configured as an output, the serial clock is provided by the dsPIC33F. When configured as an input, the serial clock must be provided by an external device. 21.2.2 CSDO PIN The Serial Data Output (CSDO) pin is configured as an output only pin when the module is enabled. The CSDO pin drives the serial bus whenever data is to be transmitted. The CSDO pin is tri-stated, or driven to `0', during CSCK periods when data is not transmitted depending on the state of the CSDOM control bit. This allows other devices to place data on the serial bus during transmission periods not used by the DCI module. The DCI module contains a buffer control unit for transferring data between the shadow buffer memory and the Serial Shift register. The buffer control unit is a simple 2-bit address counter that points to word locations in the shadow buffer memory. For the receive memory space (high address portion of DCI buffer memory), the address counter is concatenated with a `0' in the MSb location to form a 3-bit address. For the transmit memory space (high portion of DCI buffer memory), the address counter is concatenated with a `1' in the MSb location. Note: The DCI buffer control unit always accesses the same relative location in the transmit and receive buffers, so only one address counter is provided. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 261 dsPIC33F FIGURE 21-1: DCI MODULE BLOCK DIAGRAM BCG Control bits SCKD FOSC/4 Sample Rate Generator CSCK FSD Word Size Selection bits Frame Length Selection bits DCI Mode Selection bits 16-bit Data Bus Frame Synchronization Generator COFS Receive Buffer Registers w/Shadow DCI Buffer Control Unit 15 Transmit Buffer Registers w/Shadow DCI Shift Register 0 CSDI CSDO DS70165E-page 262 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 21.3 21.3.1 DCI Module Operation MODULE ENABLE 21.3.4 FRAME SYNC MODE CONTROL BITS The DCI module is enabled or disabled by setting/ clearing the DCIEN control bit in the DCICON1 SFR. Clearing the DCIEN control bit has the effect of resetting the module. In particular, all counters associated with CSCK generation, frame sync and the DCI buffer control unit are reset. The DCI clocks are shut down when the DCIEN bit is cleared. When enabled, the DCI controls the data direction for the four I/O pins associated with the module. The PORT, LAT and TRIS register values for these I/O pins are overridden by the DCI module when the DCIEN bit is set. It is also possible to override the CSCK pin separately when the bit clock generator is enabled. This permits the bit clock generator to operate without enabling the rest of the DCI module. The type of frame sync signal is selected using the Frame Synchronization mode control bits (COFSM<1:0>) in the DCICON1 SFR. The following operating modes can be selected: * * * * Multi-Channel mode I2S mode AC-Link mode (16-bit) AC-Link mode (20-bit) The operation of the COFSM control bits depends on whether the DCI module generates the frame sync signal as a master device, or receives the frame sync signal as a slave device. The master device in a DSP/Codec pair is the device that generates the frame sync signal. The frame sync signal initiates data transfers on the CSDI and CSDO pins and usually has the same frequency as the data sample rate (COFS). The DCI module is a frame sync master if the COFSD control bit is cleared and is a frame sync slave if the COFSD control bit is set. 21.3.2 WORD SIZE SELECTION BITS The WS<3:0> word size selection bits in the DCICON2 SFR determine the number of bits in each DCI data word. Essentially, the WS<3:0> bits determine the counting period for a 4-bit counter clocked from the CSCK signal. Any data length, up to 16-bits, may be selected. The value loaded into the WS<3:0> bits is one less the desired word length. For example, a 16-bit data word size is selected when WS<3:0> = 1111. Note: These WS<3:0> control bits are used only in the Multi-Channel and I2S modes. These bits have no effect in AC-Link mode since the data slot sizes are fixed by the protocol. 21.3.5 MASTER FRAME SYNC OPERATION When the DCI module is operating as a frame sync master device (COFSD = 0), the COFSM mode bits determine the type of frame sync pulse that is generated by the frame sync generator logic. A new COFS signal is generated when the frame sync generator resets to `0'. In the Multi-Channel mode, the frame sync pulse is driven high for the CSCK period to initiate a data transfer. The number of CSCK cycles between successive frame sync pulses will depend on the word size and frame sync generator control bits. A timing diagram for the frame sync signal in Multi-Channel mode is shown in Figure 21-2. In the AC-Link mode of operation, the frame sync signal has a fixed period and duty cycle. The AC-Link frame sync signal is high for 16 CSCK cycles and is low for 240 CSCK cycles. A timing diagram with the timing details at the start of an AC-Link frame is shown in Figure 21-3. In the I2S mode, a frame sync signal having a 50% duty cycle is generated. The period of the I2S frame sync signal in CSCK cycles is determined by the word size and frame sync generator control bits. A new I2S data transfer boundary is marked by a high-to-low or a low-to-high transition edge on the COFS pin. 21.3.3 FRAME SYNC GENERATOR The frame sync generator (COFSG) is a 4-bit counter that sets the frame length in data words. The frame sync generator is incremented each time the word size counter is reset (refer to Section 21.3.2 "Word Size Selection Bits"). The period for the frame synchronization generator is set by writing the COFSG<3:0> control bits in the DCICON2 SFR. The COFSG period in clock cycles is determined by the following formula: EQUATION 21-1: COFSG PERIOD Frame Length = Word Length * (FSG Value + 1) Frame lengths, up to 16 data words, may be selected. The frame length in CSCK periods can vary up to a maximum of 256 depending on the word size that is selected. Note: The COFSG control bits will have no effect in AC-Link mode since the frame length is set to 256 CSCK periods by the protocol. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 263 dsPIC33F 21.3.6 SLAVE FRAME SYNC OPERATION When the DCI module is operating as a frame sync slave (COFSD = 1), data transfers are controlled by the Codec device attached to the DCI module. The COFSM control bits control how the DCI module responds to incoming COFS signals. In the Multi-Channel mode, a new data frame transfer will begin one CSCK cycle after the COFS pin is sampled high (see Figure 21-2). The pulse on the COFS pin resets the frame sync generator logic. In the I2S mode, a new data word will be transferred one CSCK cycle after a low-to-high or a high-to-low transition is sampled on the COFS pin. A rising or falling edge on the COFS pin resets the frame sync generator logic. In the AC-Link mode, the tag slot and subsequent data slots for the next frame will be transferred one CSCK cycle after the COFS pin is sampled high. The COFSG and WS bits must be configured to provide the proper frame length when the module is operating in the Slave mode. Once a valid frame sync pulse has been sampled by the module on the COFS pin, an entire data frame transfer will take place. The module will not respond to further frame sync pulses until the data frame transfer has completed. FIGURE 21-2: FRAME SYNC TIMING, MULTI-CHANNEL MODE CSCK COFS CSDI/CSDO MSb LSb FIGURE 21-3: FRAME SYNC TIMING, AC-LINK START-OF-FRAME BIT_CLK CSDO or CSDI S12 S12 S12 Tag Tag Tag bit 2 bit 1 LSb MSb bit 14 bit 13 SYNC FIGURE 21-4: I2S INTERFACE FRAME SYNC TIMING CSCK CSDI or CSDO MSb LSb MSb LSb WS Note: A 5-bit transfer is shown here for illustration purposes. The I2S protocol does not specify word length - this will be system dependent. DS70165E-page 264 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 21.3.7 BIT CLOCK GENERATOR EQUATION 21-2: BIT CLOCK FREQUENCY FCY 2 The DCI module has a dedicated 12-bit time base that produces the bit clock. The bit clock rate (period) is set by writing a non-zero 12-bit value to the BCG<11:0> control bits in the DCICON3 SFR. When the BCG<11:0> bits are set to zero, the bit clock will be disabled. If the BCG<11:0> bits are set to a nonzero value, the bit clock generator is enabled. These bits should be set to `0' and the CSCKD bit set to `1' if the serial clock for the DCI is received from an external device. The formula for the bit clock frequency is given in Equation 21-2. FBCK = * (BCG + 1) The required bit clock frequency will be determined by the system sampling rate and frame size. Typical bit clock frequencies range from 16x to 512x the converter sample rate depending on the data converter and the communication protocol that is used. To achieve bit clock frequencies associated with common audio sampling rates, the user will need to select a crystal frequency that has an `even' binary value. Examples of such crystal frequencies are listed in Table 21-1. TABLE 21-1: FS (kHz) 8 12 32 44.1 48 Note 1: 2: DEVICE FREQUENCIES FOR COMMON CODEC CSCK FREQUENCIES FCSCK/FS 256 256 32 32 64 FCSCK (MHz)(1) 2.048 3.072 1.024 1.4112 3.072 FOSC (MHZ) 8.192 6.144 8.192 5.6448 6.144 PLL 4 8 8 8 16 FCY (MIPS) 8.192 12.288 16.384 11.2896 24.576 BCG(2) 1 1 7 3 3 When the CSCK signal is applied externally (CSCKD = 1), the external clock high and low times must meet the device timing requirements. When the CSCK signal is applied externally (CSCKD = 1), the BCG<11:0> bits have no effect on the operation of the DCI module. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 265 dsPIC33F 21.3.8 SAMPLE CLOCK EDGE CONTROL BIT 21.3.11 RECEIVE SLOT ENABLE BITS The sample clock edge (CSCKE) control bit determines the sampling edge for the CSCK signal. If the CSCK bit is cleared (default), data will be sampled on the falling edge of the CSCK signal. The AC-Link protocols and most Multi-Channel formats require that data be sampled on the falling edge of the CSCK signal. If the CSCK bit is set, data will be sampled on the rising edge of CSCK. The I2S protocol requires that data be sampled on the rising edge of the CSCK signal. The RSCON SFR contains control bits that are used to enable up to 16 time slots for reception. These control bits are the RSE<15:0> bits. The size of each receive time slot is determined by the WS<3:0> word size selection bits and can vary from 1 to 16 bits. If a receive time slot is enabled via one of the RSE bits (RSEx = 1), the DCI Shift register contents will be written to the current DCI receive shadow buffer location and the buffer control unit will be incremented to point to the next buffer location. Data is not packed in the receive memory buffer locations if the selected word size is less than 16 bits. Each received slot data word is stored in a separate 16-bit buffer location. Data is always stored in a left justified format in the receive memory buffer. 21.3.9 DATA JUSTIFICATION CONTROL BIT In most applications, the data transfer begins one CSCK cycle after the COFS signal is sampled active. This is the default configuration of the DCI module. An alternate data alignment can be selected by setting the DJST control bit in the DCICON1 SFR. When DJST = 1, data transfers will begin during the same CSCK cycle when the COFS signal is sampled active. 21.3.12 SLOT ENABLE BITS OPERATION WITH FRAME SYNC 21.3.10 TRANSMIT SLOT ENABLE BITS The TSCON SFR has control bits that are used to enable up to 16 time slots for transmission. These control bits are the TSE<15:0> bits. The size of each time slot is determined by the WS<3:0> word size selection bits and can vary up to 16 bits. If a transmit time slot is enabled via one of the TSE bits (TSEx = 1), the contents of the current transmit shadow buffer location will be loaded into the DCI Shift register and the DCI buffer control unit is incremented to point to the next location. During an unused transmit time slot, the CSDO pin will drive `0's, or will be tri-stated during all disabled time slots, depending on the state of the CSDOM bit in the DCICON1 SFR. The data frame size in bits is determined by the chosen data word size and the number of data word elements in the frame. If the chosen frame size has less than 16 elements, the additional slot enable bits will have no effect. Each transmit data word is written to the 16-bit transmit buffer as left justified data. If the selected word size is less than 16 bits, then the LSbs of the transmit buffer memory will have no effect on the transmitted data. The user should write `0's to the unused LSbs of each transmit buffer location. The TSE and RSE control bits operate in concert with the DCI frame sync generator. In Master mode, a COFS signal is generated whenever the frame sync generator is reset. In Slave mode, the frame sync generator is reset whenever a COFS pulse is received. The TSE and RSE control bits allow up to 16 consecutive time slots to be enabled for transmit or receive. After the last enabled time slot has been transmitted/ received, the DCI will stop buffering data until the next occurring COFS pulse. 21.3.13 SYNCHRONOUS DATA TRANSFERS The DCI buffer control unit will be incremented by one word location whenever a given time slot has been enabled for transmission or reception. In most cases, data input and output transfers will be synchronized, which means that a data sample is received for a given channel at the same time a data sample is transmitted. Therefore, the transmit and receive buffers will be filled with equal amounts of data when a DCI interrupt is generated. In some cases, the amount of data transmitted and received during a data frame may not be equal. As an example, assume a two-word data frame is used. Furthermore, assume that data is only received during slot #0 but is transmitted during slot #0 and slot #1. In this case, the buffer control unit counter would be incremented twice during a data frame, but only one receive register location would be filled with data. DS70165E-page 266 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 21.3.14 BUFFER LENGTH CONTROL 21.3.16 TRANSMIT STATUS BITS The amount of data that is buffered between interrupts is determined by the Buffer Length (BLEN<1:0>) control bits in the DCICON2 SFR. The size of the transmit and receive buffers can vary from 1 to 4 data words using the BLEN control bits. The BLEN control bits are compared to the current value of the DCI buffer control unit address counter. When the 2 LSbs of the DCI address counter match the BLEN<1:0> value, the buffer control unit will be reset to `0'. In addition, the contents of the Receive Shadow registers are transferred to the Receive Buffer registers and the contents of the Transmit Buffer registers are transferred to the Transmit Shadow registers. Note 1: DCI can trigger a DMA data transfer. If DCI is selected as a DMA IRQ source, a DMA transfer occurs when the DCIIF bit gets set as a result of a DCI transmission or reception. 2: If DMA transfers are required, the DCI TX/RX buffer must be set to a size of 1 word (i.e., BLEN<1:0> = 00). There are two transmit status bits in the DCISTAT SFR. The TMPTY bit is set when the contents of the transmit buffer registers are transferred to the transmit shadow registers. The TMPTY bit may be polled in software to determine when the transmit buffer registers may be written. The TMPTY bit is cleared automatically by the hardware when a write to one of the four transmit buffers occurs. The TUNF bit is read-only and indicates that a transmit underflow has occurred for at least one of the transmit buffer registers that is in use. The TUNF bit is set at the time the transmit buffer registers are transferred to the transmit shadow registers. The TUNF status bit is cleared automatically when the buffer register that underflowed is written by the CPU. Note: The transmit status bits only indicate status for buffer locations that are used by the module. If the buffer length is set to less than four words, for example, the unused buffer locations will not affect the transmit status bits. 21.3.15 BUFFER ALIGNMENT WITH DATA FRAMES 21.3.17 RECEIVE STATUS BITS There is no direct coupling between the position of the AGU Address Pointer and the data frame boundaries. This means that there will be an implied assignment of each transmit and receive buffer that is a function of the BLEN control bits and the number of enabled data slots via the TSE and RSE control bits. As an example, assume that a 4-word data frame is chosen and that we want to transmit on all four time slots in the frame. This configuration would be established by setting the TSE0, TSE1, TSE2 and TSE3 control bits in the TSCON SFR. With this module setup, the TXBUF0 register would naturally be assigned to slot #0, the TXBUF1 register would naturally be assigned to slot #1, and so on. Note: When more than four time slots are active within a data frame, the user code must keep track of which time slots are to be read/written at each interrupt. In some cases, the alignment between transmit/ receive buffers and their respective slot assignments could be lost. Examples of such cases include an emulation breakpoint or a hardware trap. In these situations, the user should poll the SLOT status bits to determine what data should be loaded into the buffer registers to resynchronize the software with the DCI module. There are two receive status bits in the DCISTAT SFR. The RFUL status bit is read-only and indicates that new data is available in the receive buffers. The RFUL bit is cleared automatically when all receive buffers in use have been read by the CPU. The ROV status bit is read-only and indicates that a receive overflow has occurred for at least one of the receive buffer locations. A receive overflow occurs when the buffer location is not read by the CPU before new data is transferred from the shadow registers. The ROV status bit is cleared automatically when the buffer register that caused the overflow is read by the CPU. When a receive overflow occurs for a specific buffer location, the old contents of the buffer are overwritten. Note: The receive status bits only indicate status for buffer locations that are used by the module. If the buffer length is set to less than four words, for example, the unused buffer locations will not affect the transmit status bits. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 267 dsPIC33F 21.3.18 SLOT STATUS BITS 21.4 DCI Module Interrupts The SLOT<3:0> status bits in the DCISTAT SFR indicate the current active time slot. These bits will correspond to the value of the frame sync generator counter. The user may poll these status bits in software when a DCI interrupt occurs to determine what time slot data was last received and which time slot data should be loaded into the TXBUF registers. 21.3.19 CSDO MODE BIT The frequency of DCI module interrupts is dependent on the BLEN<1:0> control bits in the DCICON2 SFR. An interrupt to the CPU is generated each time the set buffer length has been reached and a shadow register transfer takes place. A shadow register transfer is defined as the time when the previously written TXBUF values are transferred to the transmit shadow registers and new received values in the receive shadow registers are transferred into the RXBUF registers. The CSDOM control bit controls the behavior of the CSDO pin during unused transmit slots. A given transmit time slot is unused if it's corresponding TSEx bit in the TSCON SFR is cleared. If the CSDOM bit is cleared (default), the CSDO pin will be low during unused time slot periods. This mode will be used when there are only two devices attached to the serial bus. If the CSDOM bit is set, the CSDO pin will be tri-stated during unused time slot periods. This mode allows multiple devices to share the same CSDO line in a multi-channel application. Each device on the CSDO line is configured to only transmit data during specific time slots. No two devices will transmit data during the same time slot. 21.5 21.5.1 DCI Module Operation During CPU Sleep and Idle Modes DCI MODULE OPERATION DURING CPU SLEEP MODE The DCI module has the ability to operate while in Sleep mode and wake the CPU when the CSCK signal is supplied by an external device (CSCKD = 1). The DCI module will generate an asynchronous interrupt when a DCI buffer transfer has completed and the CPU is in Sleep mode. 21.5.2 DCI MODULE OPERATION DURING CPU IDLE MODE 21.3.20 DIGITAL LOOPBACK MODE Digital Loopback mode is enabled by setting the DLOOP control bit in the DCICON1 SFR. When the DLOOP bit is set, the module internally connects the CSDO signal to CSDI. The actual data input on the CSDI I/O pin will be ignored in Digital Loopback mode. If the DCISIDL control bit is cleared (default), the module will continue to operate normally even in Idle mode. If the DCISIDL bit is set, the module will halt when Idle mode is asserted. 21.6 AC-Link Mode Operation 21.3.21 UNDERFLOW MODE CONTROL BIT When an underflow occurs, one of two actions can occur, depending on the state of the Underflow mode (UNFM) control bit in the DCICON1 SFR. If the UNFM bit is cleared (default), the module will transmit `0's on the CSDO pin during the active time slot for the buffer location. In this operating mode, the Codec device attached to the DCI module will simply be fed digital `silence'. If the UNFM control bit is set, the module will transmit the last data written to the buffer location. This operating mode permits the user to send continuous data to the Codec device without consuming CPU overhead. The AC-Link protocol is a 256-bit frame with one 16-bit data slot, followed by twelve 20-bit data slots. The DCI module has two operating modes for the AC-Link protocol. These operating modes are selected by the COFSM<1:0> control bits in the DCICON1 SFR. The first AC-Link mode is called `16-bit AC-Link mode' and is selected by setting COFSM<1:0> = 10. The second AC-Link mode is called `20-bit AC-Link mode' and is selected by setting COFSM<1:0> = 11. 21.6.1 16-BIT AC-LINK MODE In the 16-bit AC-Link mode, data word lengths are restricted to 16 bits. Note that this restriction only affects the 20-bit data time slots of the AC-Link protocol. For received time slots, the incoming data is simply truncated to 16 bits. For outgoing time slots, the four Least Significant bits of the data word are set to `0' by the module. This truncation of the time slots limits the ADC and DAC data to 16 bits but permits proper data alignment in the TXBUF and RXBUF registers. Each RXBUF and TXBUF register will contain one data time slot value. DS70165E-page 268 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 21.6.2 20-BIT AC-LINK MODE 21.7.1 The 20-bit AC-Link mode allows all bits in the data time slots to be transmitted and received but does not maintain data alignment in the TXBUF and RXBUF registers. The 20-bit AC-Link mode functions similar to the MultiChannel mode of the DCI module, except for the duty cycle of the frame synchronization signal. The AC-Link frame synchronization signal should remain high for 16 CSCK cycles and should be low for the following 240 cycles. The 20-bit mode treats each 256-bit AC-Link frame as sixteen, 16-bit time slots. In the 20-bit AC-Link mode, the module operates as if COFSG<3:0> = 1111 and WS<3:0> = 1111. The data alignment for 20-bit data slots is ignored. For example, an entire AC-Link data frame can be transmitted and received in a packed fashion by setting all bits in the TSCON and RSCON SFRs. Since the total available buffer length is 64 bits, it would take 4 consecutive interrupts to transfer the AC-Link frame. The application software must keep track of the current AC-Link frame segment. I2S FRAME AND DATA WORD LENGTH SELECTION The WS and COFSG control bits are set to produce the period for one half of an I2S data frame. That is, the frame length is the total number of CSCK cycles required for a left or right data word transfer. The BLEN bits must be set for the desired buffer length. Setting BLEN<1:0> = 01 will produce a CPU interrupt, once per I2S frame. 21.7.2 I2S DATA JUSTIFICATION As per the I2S specification, a data word transfer will, by default, begin one CSCK cycle after a transition of the WS signal. A `Most Significant bit left justified' option can be selected using the DJST control bit in the DCICON1 SFR. If DJST = 1, the I2S data transfers will be MSb left justified. The MSb of the data word will be presented on the CSDO pin during the same CSCK cycle as the rising or falling edge of the COFS signal. The CSDO pin is tri-stated after the data word has been sent. 21.7 I2S Mode Operation The DCI module is configured for I2S mode by writing a value of `01' to the COFSM<1:0> control bits in the DCICON1 SFR. When operating in the I2S mode, the DCI module will generate frame synchronization signals with a 50% duty cycle. Each edge of the frame synchronization signal marks the boundary of a new data word transfer. The user must also select the frame length and data word size using the COFSG and WS control bits in the DCICON2 SFR. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 269 dsPIC33F REGISTER 21-1: R/W-0 DCIEN bit 15 R/W-0 UNFM bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 CSDOM R/W-0 DJST U-0 -- U-0 -- U-0 -- R/W-0 DCICON1: DCI CONTROL REGISTER 1 U-0 -- R/W-0 DCISIDL U-0 -- R/W-0 DLOOP R/W-0 CSCKD R/W-0 CSCKE R/W-0 COFSD bit 8 R/W-0 bit 0 COFSM<1:0> DCIEN: DCI Module Enable bit 1 = Module is enabled 0 = Module is disabled Reserved: Read as `0' DCISIDL: DCI Stop in Idle Control bit 1 = Module will halt in CPU Idle mode 0 = Module will continue to operate in CPU Idle mode Reserved: Read as `0' DLOOP: Digital Loopback Mode Control bit 1 = Digital Loopback mode is enabled. CSDI and CSDO pins internally connected. 0 = Digital Loopback mode is disabled CSCKD: Sample Clock Direction Control bit 1 = CSCK pin is an input when DCI module is enabled 0 = CSCK pin is an output when DCI module is enabled CSCKE: Sample Clock Edge Control bit 1 = Data changes on serial clock falling edge, sampled on serial clock rising edge 0 = Data changes on serial clock rising edge, sampled on serial clock falling edge COFSD: Frame Synchronization Direction Control bit 1 = COFS pin is an input when DCI module is enabled 0 = COFS pin is an output when DCI module is enabled UNFM: Underflow Mode bit 1 = Transmit last value written to the transmit registers on a transmit underflow 0 = Transmit `0's on a transmit underflow CSDOM: Serial Data Output Mode bit 1 = CSDO pin will be tri-stated during disabled transmit time slots 0 = CSDO pin drives `0's during disabled transmit time slots DJST: DCI Data Justification Control bit 1 = Data transmission/reception is begun during the same serial clock cycle as the frame synchronization pulse 0 = Data transmission/reception is begun one serial clock cycle after frame synchronization pulse Reserved: Read as `0' COFSM<1:0>: Frame Sync Mode bits 11 = 20-bit AC-Link mode 10 = 16-bit AC-Link mode 01 = I2S Frame Sync mode 00 = Multi-Channel Frame Sync mode bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4-2 bit 1-0 DS70165E-page 270 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 21-2: U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-10 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 COFSG<2:0> R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 DCICON2: DCI CONTROL REGISTER 2 U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 U-0 -- R/W-0 COFSG3 bit 8 R/W-0 bit 0 BLEN<1:0> WS<3:0> Reserved: Read as `0' BLEN<1:0>: Buffer Length Control bits 11 = Four data words will be buffered between interrupts 10 = Three data words will be buffered between interrupts 01 = Two data words will be buffered between interrupts 00 = One data word will be buffered between interrupts Reserved: Read as `0' COFSG<3:0>: Frame Sync Generator Control bits 1111 = Data frame has 16 words *** 0010 = Data frame has 3 words 0001 = Data frame has 2 words 0000 = Data frame has 1 word Reserved: Read as `0' WS<3:0>: DCI Data Word Size bits 1111 = Data word size is 16 bits *** 0100 = Data word size is 5 bits 0011 = Data word size is 4 bits 0010 = Invalid Selection. Do not use. Unexpected results may occur. 0001 = Invalid Selection. Do not use. Unexpected results may occur. 0000 = Invalid Selection. Do not use. Unexpected results may occur. bit 9 bit 8-5 bit 4 bit 3-0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 271 dsPIC33F REGISTER 21-3: U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCICON3: DCI CONTROL REGISTER 3 U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 BCG<11:8> BCG<7:0> Reserved: Read as `0' BCG<11:0>: DCI bit Clock Generator Control bits DS70165E-page 272 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 21-4: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R-0 ROV R-0 RFUL R-0 TUNF R-0 TMPTY bit 0 DCISTAT: DCI STATUS REGISTER U-0 -- U-0 -- U-0 -- R-0 R-0 R-0 R-0 bit 8 SLOT<3:0> Reserved: Read as `0' SLOT<3:0>: DCI Slot Status bits 1111 = Slot #15 is currently active *** 0010 = Slot #2 is currently active 0001 = Slot #1 is currently active 0000 = Slot #0 is currently active Reserved: Read as `0' ROV: Receive Overflow Status bit 1 = A receive overflow has occurred for at least one receive register 0 = A receive overflow has not occurred RFUL: Receive Buffer Full Status bit 1 = New data is available in the receive registers 0 = The receive registers have old data TUNF: Transmit Buffer Underflow Status bit 1 = A transmit underflow has occurred for at least one transmit register 0 = A transmit underflow has not occurred TMPTY: Transmit Buffer Empty Status bit 1 = The transmit registers are empty 0 = The transmit registers are not empty bit 7-4 bit 3 bit 2 bit 1 bit 0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 273 dsPIC33F REGISTER 21-5: R/W-0 RSE15 bit 15 R/W-0 RSE7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 RSE6 R/W-0 RSE5 R/W-0 RSE4 R/W-0 RSE3 R/W-0 RSE2 R/W-0 RSE1 RSCON: DCI RECEIVE SLOT CONTROL REGISTER R/W-0 RSE14 R/W-0 RSE13 R/W-0 RSE12 R/W-0 RSE11 R/W-0 RSE10 R/W-0 RSE9 R/W-0 RSE8 bit 8 R/W-0 RSE0 bit 0 RSE<15:0>: Receive Slot Enable bits 1 = CSDI data is received during the individual time slot n 0 = CSDI data is ignored during the individual time slot n REGISTER 21-6: R/W-0 TSE15 bit 15 R/W-0 TSE7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 TSCON: DCI TRANSMIT SLOT CONTROL REGISTER R/W-0 TSE14 R/W-0 TSE13 R/W-0 TSE12 R/W-0 TSE11 R/W-0 TSE10 R/W-0 TSE9 R/W-0 TSE8 bit 8 R/W-0 TSE6 R/W-0 TSE5 R/W-0 TSE4 R/W-0 TSE3 R/W-0 TSE2 R/W-0 TSE1 R/W-0 TSE0 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TSE<15:0>: Transmit Slot Enable Control bits 1 = Transmit buffer contents are sent during the individual time slot n 0 = CSDO pin is tri-stated or driven to logic `0', during the individual time slot, depending on the state of the CSDOM bit DS70165E-page 274 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 22.0 10-BIT/12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). 22.2 1. ADC Initialization The following configuration steps should be performed. Configure the ADC module: a) Select port pins as analog inputs (ADxPCFGH<15:0> or ADxPCFGL<15:0>) b) Select voltage reference source to match expected range on analog inputs (ADxCON2<15:13>) c) Select the analog conversion clock to match desired data rate with processor clock (ADxCON3<5:0>) d) Determine how many S/H channels will be used (ADxCON2<9:8> and ADxPCFGH<15:0> or ADxPCFGL<15:0>) e) Select the appropriate sample/conversion sequence (ADxCON1<7:5> and ADxCON3<12:8>) f) Select how conversion results are presented in the buffer (ADxCON1<9:8>) g) Turn on ADC module (ADxCON1<15>) Configure ADC interrupt (if required): a) Clear the ADxIF bit b) Select ADC interrupt priority Note: The dsPIC33F devices have up to 32 ADC input channels. These devices also have up to 2 ADC modules (ADCx, where `x' = 1 or 2), each with its own set of Special Function Registers. The AD12B bit (ADxCON1<10>) allows each of the ADC modules to be configured by the user as either a 10-bit, 4-sample/hold ADC (default configuration) or a 12-bit, 1-sample/hold ADC. Note: The ADC module needs to be disabled before modifying the AD12B bit. 22.1 Key Features 2. The 10-bit ADC configuration has the following key features: * * * * * * * * * * Successive Approximation (SAR) conversion Conversion speeds of up to 1.1 Msps Up to 32 analog input pins External voltage reference input pins Simultaneous sampling of up to four analog input pins Automatic Channel Scan mode Selectable conversion trigger source Selectable Buffer Fill modes Four result alignment options (signed/unsigned, fractional/integer) Operation during CPU Sleep and Idle modes 22.3 ADC and DMA If more than one conversion result needs to be buffered before triggering an interrupt, DMA data transfers can be used. Both ADC1 and ADC2 can trigger a DMA data transfer. If ADC1 or ADC2 is selected as the DMA IRQ source, a DMA transfer occurs when the AD1IF or AD2IF bit gets set as a result of an ADC1 or ADC2 sample conversion sequence. The SMPI<3:0> bits (ADxCON2<5:2>) are used to select how often the DMA RAM buffer pointer is incremented. The ADDMABM bit (ADxCON1<12>) determines how the conversion results are filled in the DMA RAM buffer area being used for ADC. If this bit is set, DMA buffers are written in the order of conversion. The module will provide an address to the DMA channel that is the same as the address used for the non-DMA stand-alone buffer. If the ADDMABM bit is cleared, then DMA buffers are written in Scatter/Gather mode. The module will provide a scatter/gather address to the DMA channel, based on the index of the analog input and the size of the DMA buffer. The 12-bit ADC configuration supports all the above features, except: * In the 12-bit configuration, conversion speeds of up to 500 ksps are supported * There is only 1 sample/hold amplifier in the 12-bit configuration, so simultaneous sampling of multiple channels is not supported. Depending on the particular device pinout, the ADC can have up to 32 analog input pins, designated AN0 through AN31. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs may be shared with other analog input pins. The actual number of analog input pins and external voltage reference input configuration will depend on the specific device. Refer to the device data sheet for further details. A block diagram of the ADC is shown in Figure 22-1. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 275 dsPIC33F FIGURE 22-1: VREF+(1) AVSS VREF-(1) ADC1 MODULE BLOCK DIAGRAM AVDD AN0 AN0 AN3 AN6 AN9 VREF- + S/H CH1(2) ADC1 AN1 AN1 AN4 AN7 AN10 VREF- + S/H CH2(2) Conversion Result Conversion Logic AN2 AN2 AN5 AN8 AN11 VREF00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 + S/H CH3(2) CH1,CH2, CH3,CH0 Sample/Sequence Control Sample AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 Input Switches Input MUX Control AN30 AN31 11110 11111 VREFAN1 + S/H CH0 Note 1: 2: VREF+, VREF- inputs may be multiplexed with other analog inputs. See device data sheet for details. Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. DS70165E-page 276 Preliminary (c) 2007 Microchip Technology Inc. Bus Interface 16-bit ADC Output Buffer Data Format dsPIC33F FIGURE 22-2: VREF+(2) AVSS VREF-(2) ADC2 MODULE BLOCK DIAGRAM(1) AVDD AN0 AN0 AN3 AN6 AN9 VREF- + S/H CH1(3) ADC2 AN1 AN1 AN4 AN7 AN10 VREF- + S/H CH2(3) Conversion Result Conversion Logic AN2 AN2 AN5 AN8 AN11 VREF00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 + S/H CH3(3) CH1,CH2, CH3,CH0 Sample/Sequence Control Sample AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 Input Switches Input MUX Control AN14 AN15 11110 11111 VREFAN1 + S/H CH0 Note 1: 2: 3: On devices with two ADC modules, AN0-AN15 can be read by either ADC1, ADC2 or both ADCs. VREF+, VREF- inputs may be multiplexed with other analog inputs. See device data sheet for details. Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 277 Bus Interface 16-bit ADC Output Buffer Data Format dsPIC33F EQUATION 22-1: ADC CONVERSION CLOCK PERIOD TAD = TCY(ADCS + 1) ADCS = TAD -1 TCY FIGURE 22-3: Output Code ADC TRANSFER FUNCTION (10-BIT EXAMPLE) 11 1111 1111 (= 1023) 11 1111 1110 (= 1022) 10 0000 0011 (= 515) 10 0000 0010 (= 514) 10 0000 0001 (= 513) 10 0000 0000 (= 512) 01 1111 1111 (= 511) 01 1111 1110 (= 510) 01 1111 1101 (= 509) 00 0000 0001 (= 1) 00 0000 0000 (= 0) VREFL VREFL + VREFH - VREFL 1024 VREFL + 512 * (VREFH - VREFL) 1024 VREFL + 1023 * (VREFH - VREFL) 1024 (VINH - VINL) VREFH FIGURE 22-4: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADxCON3<15> ADC Internal RC Clock ADxCON3<5:0> 6 ADC Conversion Clock Multiplier 1, 2, 3, 4, 5,..., 64 0 TAD 1 TOSC (1) TCY X2 1. Refer to Figure 8-2 for the derivation of FOSC when the PLL is enabled. If the PLL is not used, FOSC is equal to the clock source frequency. Tosc = 1/Fosc. DS70165E-page 278 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 22-1: R/W-0 ADON bit 15 R/W-0 R/W-0 SSRC<2:0> bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HC = Cleared by hardware W = Writable bit `1' = Bit is set HS = Set by hardware U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 U-0 -- R/W-0 SIMSAM R/W-0 ASAM R/W-0 HC,HS SAMP ADxCON1: ADCx CONTROL REGISTER 1 (where x = 1 or 2) U-0 -- R/W-0 ADSIDL R/W-0 ADDMABM U-0 -- R/W-0 AD12B R/W-0 R/W-0 bit 8 R/C-0 HC, HS DONE bit 0 FORM<1:0> ADON: ADC Operating Mode bit 1 = ADC module is operating 0 = ADC is off Unimplemented: Read as `0' ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode ADDMABM: DMA Buffer Build Mode bit 1 = DMA buffers are written in the order of conversion. The module will provide an address to the DMA channel that is the same as the address used for the non-DMA stand-alone buffer. 0 = DMA buffers are written in Scatter/Gather mode. The module will provide a scatter/gather address to the DMA channel, based on the index of the analog input and the size of the DMA buffer. Unimplemented: Read as `0' AD12B: 10-bit or 12-bit Operation Mode bit 1 = 12-bit, 1-channel ADC operation 0 = 10-bit, 4-channel ADC operation FORM<1:0>: Data Output Format bits For 10-bit operation: 11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s = .NOT.d<9>) 10 = Fractional (DOUT = dddd dddd dd00 0000) 01 = Signed integer (DOUT = ssss sssd dddd dddd, where s = .NOT.d<9>) 00 = Integer (DOUT = 0000 00dd dddd dddd) For 12-bit operation: 11 = Signed fractional (DOUT = sddd dddd dddd 0000, where s = .NOT.d<11>) 10 = Fractional (DOUT = dddd dddd dddd 0000) 01 = Signed Integer (DOUT = ssss sddd dddd dddd, where s = .NOT.d<11>) 00 = Integer (DOUT = 0000 dddd dddd dddd) SSRC<2:0>: Sample Clock Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = Reserved 101 = Reserved 100 = Reserved 011 = MPWM interval ends sampling and starts conversion 010 = GP timer (Timer3 for ADC1, Timer5 for ADC2) compare ends sampling and starts conversion 001 = Active transition on INTx pin ends sampling and starts conversion 000 = Clearing sample bit ends sampling and starts conversion Unimplemented: Read as `0' bit 14 bit 13 bit 12 bit 11 bit 10 bit 9-8 bit 7-5 bit 4 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 279 dsPIC33F REGISTER 22-1: bit 3 ADxCON1: ADCx CONTROL REGISTER 1 (CONTINUED)(where x = 1 or 2) SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 or 1x) When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as `0' 1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01) 0 = Samples multiple channels individually in sequence ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion. SAMP bit is auto-set. 0 = Sampling begins when SAMP bit is set SAMP: ADC Sample Enable bit 1 = ADC sample/hold amplifiers are sampling 0 = ADC sample/hold amplifiers are holding If ASAM = 0, software may write `1' to begin sampling. Automatically set by hardware if ASAM = 1. If SSRC = 000, software may write `0' to end sampling and start conversion. If SSRC 000, automatically cleared by hardware to end sampling and start conversion. DONE: ADC Conversion Status bit 1 = ADC conversion cycle is completed. 0 = ADC conversion not started or in progress Automatically set by hardware when ADC conversion is complete. Software may write `0' to clear DONE status (software not allowed to write `1'). Clearing this bit will NOT affect any operation in progress. Automatically cleared by hardware at start of a new conversion. bit 2 bit 1 bit 0 DS70165E-page 280 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 22-2: R/W-0 bit 15 R-0 BUFS bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFM ADxCON2: ADCx CONTROL REGISTER 2 (where x = 1 or 2) R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 CSCNA R/W-0 R/W-0 bit 8 R/W-0 ALTS bit 0 CHPS<1:0> VCFG<2:0> SMPI<3:0> VCFG<2:0>: Converter Voltage Reference Configuration bits ADREF+ 000 001 010 011 1xx AVDD External VREF+ AVDD External VREF+ AVDD ADREFAVSS AVSS External VREFExternal VREFAvss bit 12-11 bit 10 Unimplemented: Read as `0' CSCNA: Scan Input Selections for CH0+ during Sample A bit 1 = Scan inputs 0 = Do not scan inputs CHPS<1:0>: Selects Channels Utilized bits When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as `0' 1x = Converts CH0, CH1, CH2 and CH3 01 = Converts CH0 and CH1 00 = Converts CH0 BUFS: Buffer Fill Status bit (only valid when BUFM = 1) 1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7 0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF Unimplemented: Read as `0' SMPI<3:0>: Selects Increment Rate for DMA Addresses bits or number of sample/conversion operations per interrupt. 1111 = Increments the DMA address or generates interrupt after completion of every 16th sample/conversion operation 1110 = Increments the DMA address or generates interrupt after completion of every 15th sample/conversion operation *** 0001 = Increments the DMA address or generates interrupt after completion of every 2nd sample/conversion operation 0000 = Increments the DMA address or generates interrupt after completion of every sample/conversion operation BUFM: Buffer Fill Mode Select bit 1 = Starts buffer filling at address 0x0 on first interrupt and 0x8 on next interrupt 0 = Always starts filling buffer at address 0x0 bit 9-8 bit 7 bit 6 bit 5-2 bit 1 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 281 dsPIC33F REGISTER 22-2: bit 0 ADxCON2: ADCx CONTROL REGISTER 2 (CONTINUED) (where x = 1 or 2) ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A DS70165E-page 282 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 22-3: R/W-0 ADRC bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADxCON3: ADCx CONTROL REGISTER 3 U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 SAMC<4:0> bit 8 R/W-0 bit 0 R/W-0 R/W-0 ADCS<5:0> ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock 0 = Clock derived from system clock Unimplemented: Read as `0' SAMC<4:0>: Auto Sample Time bits 11111 = 31 TAD *** 00001 = 1 TAD 00000 = 0 TAD Unimplemented: Read as `0' ADCS<5:0>: ADC Conversion Clock Select bits 111111 = TCY * (ADCS<7:0> + 1) = 64 * TCY = TAD *** 000010 = TCY * (ADCS<7:0> + 1) = 3 * TCY = TAD 000001 = TCY * (ADCS<7:0> + 1) = 2 * TCY = TAD 000000 = TCY * (ADCS<7:0> + 1) = 1 * TCY = TAD bit 14-13 bit 12-8 bit 7-6 bit 5-0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 283 dsPIC33F REGISTER 22-4: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 DMABL<2:0> bit 0 ADxCON4: ADCx CONTROL REGISTER 4 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 Unimplemented: Read as `0' DMABL<2:0>: Selects Number of DMA Buffer Locations per Analog Input bits 111 = Allocates 128 words of buffer to each analog input 110 = Allocates 64 words of buffer to each analog input 101 = Allocates 32 words of buffer to each analog input 100 = Allocates 16 words of buffer to each analog input 011 = Allocates 8 words of buffer to each analog input 010 = Allocates 4 words of buffer to each analog input 001 = Allocates 2 words of buffer to each analog input 000 = Allocates 1 word of buffer to each analog input DS70165E-page 284 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 22-5: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-9 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 ADxCHS123: ADCx INPUT CHANNEL 1, 2, 3 SELECT REGISTER U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 CH123SB bit 8 R/W-0 CH123SA bit 0 CH123NB<1:0> CH123NA<1:0> Unimplemented: Read as `0' CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits When AD12B = 1, CHxNB is: U-0, Unimplemented, Read as `0' 11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8 0x = CH1, CH2, CH3 negative input is VREFCH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as `0' 1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 Unimplemented: Read as `0' CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits When AD12B = 1, CHxNA is: U-0, Unimplemented, Read as `0' 11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8 0x = CH1, CH2, CH3 negative input is VREFCH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as `0' 1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 bit 8 bit 7-3 bit 2-1 bit 0 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 285 dsPIC33F REGISTER 22-6: R/W-0 CH0NB bit 15 R/W-0 CH0NA bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-13 bit 12-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 CH0SA<4:0> bit 0 R/W-0 ADxCHS0: ADCx INPUT CHANNEL 0 SELECT REGISTER U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 CH0SB<4:0> bit 8 R/W-0 R/W-0 R/W-0 CH0NB: Channel 0 Negative Input Select for Sample B bit Same definition as bit 7. Unimplemented: Read as `0' CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits Same definition as bit<4:0>. CH0NA: Channel 0 Negative Input Select for Sample A bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VREFUnimplemented: Read as `0' CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits 11111 = Channel 0 positive input is AN31 11110 = Channel 0 positive input is AN30 *** 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 bit 6-5 bit 4-0 DS70165E-page 286 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F REGISTER 22-7: R/W-0 CSS31 bit 15 R/W-0 CSS23 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 CSS22 R/W-0 CSS21 R/W-0 CSS20 R/W-0 CSS19 R/W-0 CSS18 R/W-0 CSS17 ADxCSSH: ADCx INPUT SCAN SELECT REGISTER HIGH(1) R/W-0 CSS30 R/W-0 CSS29 R/W-0 CSS28 R/W-0 CSS27 R/W-0 CSS26 R/W-0 CSS25 R/W-0 CSS24 bit 8 R/W-0 CSS16 bit 0 CSS<31:16>: ADC Input Scan Selection bits 1 = Select ANx for input scan 0 = Skip ANx for input scan On devices without 32 analog inputs, all ADxCSSL bits may be selected by user. However, inputs selected for scan without a corresponding input on device will convert ADREF-. Note 1: REGISTER 22-8: R/W-0 CSS15 bit 15 R/W-0 CSS7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 ADxCSSL: ADCx INPUT SCAN SELECT REGISTER LOW(1) R/W-0 CSS14 R/W-0 CSS13 R/W-0 CSS12 R/W-0 CSS11 R/W-0 CSS10 R/W-0 CSS9 R/W-0 CSS8 bit 8 R/W-0 CSS6 R/W-0 CSS5 R/W-0 CSS4 R/W-0 CSS3 R/W-0 CSS2 R/W-0 CSS1 R/W-0 CSS0 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CSS<15:0>: ADC Input Scan Selection bits 1 = Select ANx for input scan 0 = Skip ANx for input scan On devices without 16 analog inputs, all ADxCSSL bits may be selected by user. However, inputs selected for scan without a corresponding input on device will convert ADREF-. Note 1: (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 287 dsPIC33F REGISTER 22-9: R/W-0 PCFG31 bit 15 R/W-0 PCFG23 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 PCFG22 R/W-0 PCFG21 R/W-0 PCFG20 R/W-0 PCFG19 R/W-0 PCFG18 R/W-0 PCFG17 AD1PCFGH: ADC1 PORT CONFIGURATION REGISTER HIGH(1,2) R/W-0 R/W-0 PCFG29 R/W-0 PCFG28 R/W-0 PCFG27 R/W-0 PCFG26 R/W-0 PCFG25 R/W-0 PCFG24 bit 8 R/W-0 PCFG16 bit 0 PCFG30 PCFG<31:16>: ADC Port Configuration Control bits 1 = Port pin in Digital mode, port read input enabled, ADC input multiplexor connected to AVSS 0 = Port pin in Analog mode, port read input disabled, ADC samples pin voltage On devices without 32 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on ports without a corresponding input on device. ADC2 only supports analog inputs AN0-AN15; therefore, no ADC2 port Configuration register exists. Note 1: 2: REGISTER 22-10: ADxPCFGL: ADCx PORT CONFIGURATION REGISTER LOW(1,2) R/W-0 PCFG15 bit 15 R/W-0 PCFG7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 PCFG6 R/W-0 PCFG5 R/W-0 PCFG4 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG14 R/W-0 PCFG13 R/W-0 PCFG12 R/W-0 PCFG11 R/W-0 PCFG10 R/W-0 PCFG9 R/W-0 PCFG8 bit 8 R/W-0 PCFG0 bit 0 PCFG<15:0>: ADC Port Configuration Control bits 1 = Port pin in Digital mode, port read input enabled, ADC input multiplexor connected to AVSS 0 = Port pin in Analog mode, port read input disabled, ADC samples pin voltage On devices without 16 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on ports without a corresponding input on device. On devices with two analog-to-digital modules, both AD1PCFGL and AD2PCFGL will affect the configuration of port pins multiplexed with AN0-AN15. Note 1: 2: DS70165E-page 288 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 23.0 Note: SPECIAL FEATURES This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). The device Configuration register map is shown in Table 23-1. The individual Configuration bit descriptions for the FBS, FSS, FGS, FOSCSEL, FOSC, FWDT, FPOR and FICD Configuration registers are shown in Table 23-2. Note that address 0xF80000 is beyond the user program memory space. In fact, it belongs to the configuration memory space (0x800000-0xFFFFFF) which can only be accessed using table reads and table writes. The upper byte of all device Configuration registers should always be `1111 1111'. This makes them appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing `1's to these locations has no effect on device operation. To prevent inadvertent configuration changes during code execution, all programmable Configuration bits are write-once. After a bit is initially programmed during a power cycle, it cannot be written to again. Changing a device configuration requires that power to the device be cycled. dsPIC33F devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: * * * * * * Flexible Configuration Watchdog Timer (WDT) Code Protection and CodeGuardTM Security JTAG Boundary Scan Interface In-Circuit Serial ProgrammingTM (ICSPTM) In-Circuit Emulation 23.1 Configuration Bits The Configuration bits can be programmed (read as `0'), or left unprogrammed (read as `1'), to select various device configurations. These bits are mapped starting at program memory location 0xF80000. TABLE 23-1: Address 0xF80000 FBS 0xF80002 FSS 0xF8004 0xF8006 0xF8008 0xF800A 0xF800C 0xF800E 0xF8010 0xF8012 0xF8014 0xF8016 Note 1: 2: 3: 4: FGS DEVICE CONFIGURATION REGISTER MAP Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 BSS<2:0> SSS<2:0> Bit 1 Bit 0 BWRP SWRP GSS0 GWRP RBS<1:0> RSS<1:0> -- IESO FWDTEN PWMPIN(1) -- -- -- -- -- -- -- -- -- TEMP -- -- LPOL(1) -- -- -- (2) GSS1 OSCIOFNC FOSCSEL FOSC FWDT FPOR RESERVED3 FUID0 FUID1 FUID2 FUID3 FCKSM<1:0> WINDIS HPOL(1) -- WDTPRE POSCMD<1:0> WDTPOST<3:0> FPWRT<2:0> -- Reserved User Unit ID Byte 0 User Unit ID Byte 1 User Unit ID Byte 2 User Unit ID Byte 3 On the dsPIC33F General Purpose Family devices (dsPIC33FJXXXGPXXX), these bits are reserved (read as `1' and must be programmed as `1'). These reserved bits read as `1' and must be programmed as `1'. Unimplemented bits are read as `0'. This reserved bit is a read-only copy of the GCP bit. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 289 dsPIC33F TABLE 23-2: Bit Field BWRP dsPIC33F CONFIGURATION BITS DESCRIPTION Register FBS Description Boot Segment Program Flash Write Protection 1 = Boot segment may be written 0 = Boot segment is write-protected Boot Segment Program Flash Code Protection Size X11 = No Boot program Flash segment Boot space is 1K IW less VS 110 = Standard security; boot program Flash segment starts at End of VS, ends at 0007FEh 010 = High security; boot program Flash segment starts at End of VS, ends at 0007FEh Boot space is 4K IW less VS 101 = Standard security; boot program Flash segment starts at End of VS, ends at 001FFEh 001 = High security; boot program Flash segment starts at End of VS, ends at 001FFEh Boot space is 8K IW less VS 100 = Standard security; boot program Flash segment starts at End of VS, ends at 003FFEh 000 = High security; boot program Flash segment starts at End of VS, ends at 003FFEh BSS<2:0> FBS RBS<1:0> FBS Boot Segment RAM Code Protection 10 = No Boot RAM defined 10 = Boot RAM is 128 Bytes 01 = Boot RAM is 256 Bytes 00 = Boot RAM is 1024 Bytes Secure Segment Program Flash Write Protection 1 = Secure segment may be written 0 = Secure segment is write-protected. SWRP FSS DS70165E-page 290 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F TABLE 23-2: Bit Field SSS<2:0> dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED) Register FSS Description Secure Segment Program Flash Code Protection Size (FOR 128K and 256K DEVICES) X11 = No Secure program Flash segment Secure space is 8K IW less BS 110 = Standard security; secure program Flash segment starts at End of BS, ends at 0x003FFE 010 = High security; secure program Flash segment starts at End of BS, ends at 0x003FFE Secure space is 16K IW less BS 101 = Standard security; secure program Flash segment starts at End of BS, ends at 0x007FFE 001 = High security; secure program Flash segment starts at End of BS, ends at 0x007FFE Secure space is 32K IW less BS 100 = Standard security; secure program Flash segment starts at End of BS, ends at 0x00FFFE 000 = High security; secure program Flash segment starts at End of BS, ends at 0x00FFFE (FOR 64K DEVICES) X11 = No Secure program Flash segment Secure space is 4K IW less BS 110 = Standard security; secure program Flash segment starts at End of BS, ends at 0x001FFE 010 = High security; secure program Flash segment starts at End of BS, ends at 0x001FFE Secure space is 8K IW less BS 101 = Standard security; secure program Flash segment starts at End of BS, ends at 0x003FFE 001 = High security; secure program Flash segment starts at End of BS, ends at 0x003FFE Secure space is 16K IW less BS 100 = Standard security; secure program Flash segment starts at End of BS, ends at 007FFEh 000 = High security; secure program Flash segment starts at End of BS, ends at 0x007FFE RSS<1:0> FSS Secure Segment RAM Code Protection 10 = No Secure RAM defined 10 = Secure RAM is 256 Bytes less BS RAM 01 = Secure RAM is 2048 Bytes less BS RAM 00 = Secure RAM is 4096 Bytes less BS RAM General Segment Code-Protect bit 11 = User program memory is not code-protected 10 = Standard security; general program Flash segment starts at End of SS, ends at EOM 0x = High security; general program Flash segment starts at End of SS, ends at EOM GSS<1:0> FGS (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 291 dsPIC33F TABLE 23-2: Bit Field GWRP dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED) Register FGS Description General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected Two-speed Oscillator Start-up Enable bit 1 = Start-up device with FRC, then automatically switch to the user-selected oscillator source when ready 0 = Start-up device with user-selected oscillator source Temperature Protection Enable bit 1 = Temperature protection disabled 0 = Temperature protection enabled Initial Oscillator Source Selection bits 111 = Internal Fast RC (FRC) oscillator with postscaler 110 = Internal Fast RC (FRC) oscillator with divide-by-16 101 = LPRC oscillator 100 = Secondary (LP) oscillator 011 = Primary (XT, HS, EC) oscillator with PLL 010 = Primary (XT, HS, EC) oscillator 001 = Internal Fast RC (FRC) oscillator with PLL 000 = FRC oscillator Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled OSC2 Pin Function bit (except in XT and HS modes) 1 = OSC2 is clock output 0 = OSC2 is general purpose digital I/O pin Primary Oscillator Mode Select bits 11 = Primary oscillator disabled 10 = HS Crystal Oscillator mode 01 = XT Crystal Oscillator mode 00 = EC (External Clock) mode Watchdog Timer Enable bit 1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled. Clearing the SWDTEN bit in the RCON register will have no effect.) 0 = Watchdog Timer enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register) Watchdog Timer Window Enable bit 1 = Watchdog Timer in Non-Window mode 0 = Watchdog Timer in Window mode Watchdog Timer Prescaler bit 1 = 1:128 0 = 1:32 Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 . . . 0001 = 1:2 0000 = 1:1 IESO FOSCSEL TEMP FOSCSEL FNOSC<2:0> FOSCSEL FCKSM<1:0> FOSC OSCIOFNC FOSC POSCMD<1:0> FOSC FWDTEN FWDT WINDIS FWDT WDTPRE FWDT WDTPOST FWDT DS70165E-page 292 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F TABLE 23-2: Bit Field PWMPIN dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED) Register FPOR Description Motor Control PWM Module Pin Mode bit 1 = PWM module pins controlled by PORT register at device Reset (tri-stated) 0 = PWM module pins controlled by PWM module at device Reset (configured as output pins) Motor Control PWM High Side Polarity bit 1 = PWM module high side output pins have active-high output polarity 0 = PWM module high side output pins have active-low output polarity Motor Control PWM Low Side Polarity bit 1 = PWM module low side output pins have active-high output polarity 0 = PWM module low side output pins have active-low output polarity Power-on Reset Timer Value Select bits 111 = PWRT = 128 ms 110 = PWRT = 64 ms 101 = PWRT = 32 ms 100 = PWRT = 16 ms 011 = PWRT = 8 ms 010 = PWRT = 4 ms 001 = PWRT = 2 ms 000 = PWRT = Disabled Reserved (either read as `1' and write as `1', or read as `0' and write as `0') HPOL FPOR LPOL FPOR FPWRT<2:0> FPOR Reserved -- RESERVED3, FPOR FGS, FOSCSEL, Unimplemented (read as `0', write as `0') FOSC, FWDT, FPOR 23.2 On-Chip Voltage Regulator FIGURE 23-1: All of the dsPIC33F devices power their core digital logic at a nominal 2.5V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the dsPIC33F family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator provides power to the core from the other VDD pins. When the regulator is enabled, a low-ESR (less than 5 ohms) capacitor (such as tantalum or ceramic) must be connected to the VDDCORE/VCAP pin (Figure 23-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor is provided in TABLE 26-12: "Internal Voltage Regulator Specifications" located in Section 26.1 "DC Characteristics". On a POR, it takes approximately 20 s for the on-chip voltage regulator to generate an output voltage. During this time, designated as TSTARTUP, code execution is disabled. TSTARTUP is applied every time the device resumes operation after any power-down. CONNECTIONS FOR THE ON-CHIP VOLTAGE REGULATOR(1) 3.3V dsPIC33F VDD VDDCORE/VCAP CF VSS Note 1: These are typical operating voltages. Refer to TABLE 26-12: "Internal Voltage Regulator Specifications" located in Section 26.1 "DC Characteristics" for the full operating ranges of VDD and VDDCORE. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 293 dsPIC33F 23.3 Watchdog Timer (WDT) For dsPIC33F devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the WDTPRE Configuration bit. With a 32 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPOST<3:0> Configuration bits (FWDT<3:0>) which allow the selection of a total of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. The WDT, prescaler and postscaler are reset: * On any device Reset * On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits) or by hardware (i.e., Fail-Safe Clock Monitor) * When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) * When the device exits Sleep or Idle mode to resume normal operation * By a CLRWDT instruction during normal execution If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bits (RCON<3,2>) will need to be cleared in software after the device wakes up. The WDT flag bit, WDTO (RCON<4>), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. The WDT is enabled or disabled by the FWDTEN Configuration bit in the FWDT Configuration register. When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to `0'. The WDT is enabled in software by setting the SWDTEN control bit (RCON<5>). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings. Note: If the WINDIS bit (FWDT<6>) is cleared, the CLRWDT instruction should be executed by the application software only during the last 1/4 of the WDT period. This CLRWDT window can be determined by using a timer. If a CLRWDT instruction is executed before this window, a WDT Reset occurs. FIGURE 23-2: SWDTEN FWDTEN WDT BLOCK DIAGRAM LPRC Control WDTPRE Prescaler 32.768 kHz 1 ms/4 ms WDT Counter WDTPOST<3:0> Postscaler WDT Overflow Reset Wake from Sleep LPRC Input All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode DS70165E-page 294 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 23.4 JTAG Interface 23.7 In-Circuit Debugger dsPIC33F devices implement a JTAG interface, which supports boundary scan device testing, as well as in-circuit programming. Detailed information on the interface will be provided in future revisions of the document. When MPLAB(R) ICD 2 is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the EMUCx (Emulation/Debug Clock) and EMUDx (Emulation/Debug Data) pin functions. Any 1 out of 3 pairs of debugging clock/data pins may be used: * PGC1/EMUC1 and PGD1/EMUD1 * PGC2/EMUC2 and PGD2/EMUD2 * PGC3/EMUC3 and PGD3/EMUD3 To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS, PGC, PGD and the EMUDx/EMUCx pin pair. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. 23.5 Code Protection and CodeGuardTM Security The dsPIC33F product families offer the advanced implementation of CodeGuardTM Security. CodeGuard Security enables multiple parties to securely share resources (memory, interrupts and peripherals) on a single chip. This feature helps protect individual Intellectual Property in collaborative system designs. When coupled with software encryption libraries, CodeGuardTM Security can be used to securely update Flash even when multiple IP are resident on the single chip. The code protection features vary depending on the actual dsPIC33F implemented. The following sections provide an overview of these features. The code protection features are controlled by the Configuration registers: FBS, FSS and FGS. Note: Refer to GodeGuard Security Reference Manual (DS70180) for further information on usage, configuration and operation of CodeGuard Security. 23.6 In-Circuit Serial Programming dsPIC33F family digital signal controllers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming sequence. This allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware, to be programmed. Please refer to the "dsPIC33F Flash Programming Specification" (DS70152) document for details about ICSP. Any 1 out of 3 pairs of programming clock/data pins may be used: * PGC1/EMUC1 and PGD1/EMUD1 * PGC2/EMUC2 and PGD2/EMUD2 * PGC3/EMUC3 and PGD3/EMUD3 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 295 dsPIC33F NOTES: DS70165E-page 296 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 24.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes the features of this group of dsPIC33F devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC30F Family Reference Manual" (DS70046). Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: * The W register (with or without an address modifier) or file register (specified by the value of `Ws' or `f') * The bit in the W register or file register (specified by a literal value or indirectly by the contents of register `Wb') The literal instructions that involve data movement may use some of the following operands: * A literal value to be loaded into a W register or file register (specified by the value of `k') * The W register or file register where the literal value is to be loaded (specified by `Wb' or `f') However, literal instructions that involve arithmetic or logical operations use some of the following operands: * The first source operand which is a register `Wb' without any address modifier * The second source operand which is a literal value * The destination of the result (only if not the same as the first source operand) which is typically a register `Wd' with or without an address modifier The MAC class of DSP instructions may use some of the following operands: * The accumulator (A or B) to be used (required operand) * The W registers to be used as the two operands * The X and Y address space prefetch operations * The X and Y address space prefetch destinations * The accumulator write back destination The other DSP instructions do not involve any multiplication and may include: * The accumulator to be used (required) * The source or destination operand (designated as Wso or Wdo, respectively) with or without an address modifier * The amount of shift specified by a W register `Wn' or a literal value The control instructions may use some of the following operands: * A program memory address * The mode of the table read and table write instructions The dsPIC33F instruction set is identical to that of the dsPIC30F. Most instructions are a single program memory word (24 bits). Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word, divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into five basic categories: * * * * * Word or byte-oriented operations Bit-oriented operations Literal operations DSP operations Control operations Table 24-1 shows the general symbols used in describing the instructions. The dsPIC33F instruction set summary in Table 24-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: * The first source operand which is typically a register `Wb' without any address modifier * The second source operand which is typically a register `Ws' with or without an address modifier * The destination of the result which is typically a register `Wd' with or without an address modifier However, word or byte-oriented file register instructions have two operands: * The file register specified by the value `f' * The destination, which could either be the file register `f' or the W0 register, which is denoted as `WREG' (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 297 dsPIC33F All instructions are a single word, except for certain double-word instructions, which were made doubleword instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are `0's. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. Note: For more details on the instruction set, refer to the "dsPIC30F/33F Programmer's Reference Manual" (DS70157). TABLE 24-1: Field #text (text) [text] {} SYMBOLS USED IN OPCODE DESCRIPTIONS Description Means literal defined by "text" Means "content of text" Means "the location addressed by text" Optional field or operation Register bit field Byte mode selection Double-Word mode selection Shadow register select Word mode selection (default) One of two accumulators {A, B} Accumulator write back destination address register {W13, [W13]+ = 2} 4-bit bit selection field (used in word addressed instructions) {0...15} MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Absolute address, label or expression (resolved by the linker) File register address {0x0000...0x1FFF} 1-bit unsigned literal {0,1} 4-bit unsigned literal {0...15} 5-bit unsigned literal {0...31} 8-bit unsigned literal {0...255} 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode 14-bit unsigned literal {0...16384} 16-bit unsigned literal {0...65535} 23-bit unsigned literal {0...8388608}; LSb must be `0' Field does not require an entry, may be blank DSP Status bits: AccA Overflow, AccB Overflow, AccA Saturate, AccB Saturate Program Counter 10-bit signed literal {-512...511} 16-bit signed literal {-32768...32767} 6-bit signed literal {-16...16} Base W register {W0..W15} Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Destination W register { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Dividend, Divisor working register pair (direct addressing) DS70165E-page 298 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F TABLE 24-1: Field Wm*Wm Wm*Wn Wn Wnd Wns WREG Ws Wso Wx SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Description Multiplicand and Multiplier working register pair for Square instructions {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Multiplicand and Multiplier working register pair for DSP instructions {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} One of 16 working registers {W0..W15} One of 16 destination working registers {W0..W15} One of 16 source working registers {W0..W15} W0 (working register used in file register instructions) Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } X data space prefetch address register for DSP instructions {[W8]+ = 6, [W8]+ = 4, [W8]+ = 2, [W8], [W8]- = 6, [W8]- = 4, [W8]- = 2, [W9]+ = 6, [W9]+ = 4, [W9]+ = 2, [W9], [W9]- = 6, [W9]- = 4, [W9]- = 2, [W9 + W12], none} X data space prefetch destination register for DSP instructions {W4..W7} Y data space prefetch address register for DSP instructions {[W10]+ = 6, [W10]+ = 4, [W10]+ = 2, [W10], [W10]- = 6, [W10]- = 4, [W10]- = 2, [W11]+ = 6, [W11]+ = 4, [W11]+ = 2, [W11], [W11]- = 6, [W11]- = 4, [W11]- = 2, [W11 + W12], none} Y data space prefetch destination register for DSP instructions {W4..W7} Wxd Wy Wyd (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 299 dsPIC33F TABLE 24-2: Base Instr # 1 Assembly Mnemonic ADD ADD ADD ADD ADD ADD ADD ADD 2 ADDC ADDC ADDC ADDC ADDC ADDC 3 AND AND AND AND AND AND 4 ASR ASR ASR ASR ASR ASR 5 BCLR BCLR BCLR 6 BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA 7 BSET BSET BSET 8 BSW BSW.C BSW.Z 9 BTG BTG BTG INSTRUCTION SET OVERVIEW Assembly Syntax Acc f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Wso,#Slit4,Acc f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,#bit4 Ws,#bit4 C,Expr GE,Expr GEU,Expr GT,Expr GTU,Expr LE,Expr LEU,Expr LT,Expr LTU,Expr N,Expr NC,Expr NN,Expr NOV,Expr NZ,Expr OA,Expr OB,Expr OV,Expr SA,Expr SB,Expr Expr Z,Expr Wn f,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 Description Add Accumulators f = f + WREG WREG = f + WREG Wd = lit10 + Wd Wd = Wb + Ws Wd = Wb + lit5 16-bit Signed Add to Accumulator f = f + WREG + (C) WREG = f + WREG + (C) Wd = lit10 + Wd + (C) Wd = Wb + Ws + (C) Wd = Wb + lit5 + (C) f = f .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND. Wd Wd = Wb .AND. Ws Wd = Wb .AND. lit5 f = Arithmetic Right Shift f WREG = Arithmetic Right Shift f Wd = Arithmetic Right Shift Ws Wnd = Arithmetic Right Shift Wb by Wns Wnd = Arithmetic Right Shift Wb by lit5 Bit Clear f Bit Clear Ws Branch if Carry Branch if greater than or equal Branch if unsigned greater than or equal Branch if greater than Branch if unsigned greater than Branch if less than or equal Branch if unsigned less than or equal Branch if less than Branch if unsigned less than Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Accumulator A overflow Branch if Accumulator B overflow Branch if Overflow Branch if Accumulator A saturated Branch if Accumulator B saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws DS70165E-page 300 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F TABLE 24-2: Base Instr # 10 Assembly Mnemonic BTSC BTSC BTSC 11 BTSS BTSS BTSS 12 BTST BTST BTST.C BTST.Z BTST.C BTST.Z 13 BTSTS BTSTS BTSTS.C BTSTS.Z 14 CALL CALL CALL 15 CLR CLR CLR CLR CLR 16 17 CLRWDT COM CLRWDT COM COM COM 18 CP CP CP CP 19 CP0 CP0 CP0 20 CPB CPB CPB CPB 21 22 23 24 25 26 CPSEQ CPSGT CPSLT CPSNE DAW DEC CPSEQ CPSGT CPSLT CPSNE DAW DEC DEC DEC 27 DEC2 DEC2 DEC2 DEC2 28 DISI DISI f f,WREG Ws,Wd f Wb,#lit5 Wb,Ws f Ws f Wb,#lit5 Wb,Ws Wb, Wn Wb, Wn Wb, Wn Wb, Wn Wn f f,WREG Ws,Wd f f,WREG Ws,Wd #lit14 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 Ws,#bit4 lit23 Wn f WREG Ws Acc,Wx,Wxd,Wy,Wyd,AWB Description Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Ws to C Bit Test Ws to Z Bit Test Ws (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 301 dsPIC33F TABLE 24-2: Base Instr # 29 Assembly Mnemonic DIV DIV.S DIV.SD DIV.U DIV.UD 30 31 DIVF DO DIVF DO DO 32 33 34 35 36 37 38 ED EDAC EXCH FBCL FF1L FF1R GOTO ED EDAC EXCH FBCL FF1L FF1R GOTO GOTO 39 INC INC INC INC 40 INC2 INC2 INC2 INC2 41 IOR IOR IOR IOR IOR IOR 42 43 44 LAC LNK LSR LAC LNK LSR LSR LSR LSR LSR 45 MAC MAC MAC 46 MOV MOV MOV MOV MOV MOV.b MOV MOV MOV MOV.D MOV.D 47 MOVSAC INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Wm,Wn Wm,Wn Wm,Wn Wm,Wn Wm,Wn #lit14,Expr Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd Wm*Wm,Acc,Wx,Wy,Wxd Wns,Wnd Ws,Wnd Ws,Wnd Ws,Wnd Expr Wn f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Wso,#Slit4,Acc #lit14 f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd Wm*Wn,Acc,Wx,Wxd,Wy,Wyd, AWB Wm*Wm,Acc,Wx,Wxd,Wy,Wyd f,Wn f f,WREG #lit16,Wn #lit8,Wn Wn,f Wso,Wdo WREG,f Wns,Wd Ws,Wnd Description Signed 16/16-bit Integer Divide Signed 32/16-bit Integer Divide Unsigned 16/16-bit Integer Divide Unsigned 32/16-bit Integer Divide Signed 16/16-bit Fractional Divide Do code to PC + Expr, lit14 + 1 times Do code to PC + Expr, (Wn) + 1 times Euclidean Distance (no accumulate) Euclidean Distance Swap Wns with Wnd Find Bit Change from Left (MSb) Side Find First One from Left (MSb) Side Find First One from Right (LSb) Side Go to address Go to indirect f=f+1 WREG = f + 1 Wd = Ws + 1 f=f+2 WREG = f + 2 Wd = Ws + 2 f = f .IOR. WREG WREG = f .IOR. WREG Wd = lit10 .IOR. Wd Wd = Wb .IOR. Ws Wd = Wb .IOR. lit5 Load Accumulator Link Frame Pointer f = Logical Right Shift f WREG = Logical Right Shift f Wd = Logical Right Shift Ws Wnd = Logical Right Shift Wb by Wns Wnd = Logical Right Shift Wb by lit5 Multiply and Accumulate Square and Accumulate Move f to Wn Move f to f Move f to WREG Move 16-bit literal to Wn Move 8-bit literal to Wn Move Wn to f Move Ws to Wd Move WREG to f Move Double from W(ns):W(ns + 1) to Wd Move Double from Ws to W(nd + 1):W(nd) Prefetch and store accumulator # of # of Words Cycles 1 1 1 1 1 2 2 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 18 18 18 18 18 2 2 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 Status Flags Affected N,Z,C,OV N,Z,C,OV N,Z,C,OV N,Z,C,OV N,Z,C,OV None None OA,OB,OAB, SA,SB,SAB OA,OB,OAB, SA,SB,SAB None C C C None None C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z N,Z N,Z N,Z N,Z N,Z OA,OB,OAB, SA,SB,SAB None C,N,OV,Z C,N,OV,Z C,N,OV,Z N,Z N,Z OA,OB,OAB, SA,SB,SAB OA,OB,OAB, SA,SB,SAB None N,Z N,Z None None None None N,Z None None None MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB DS70165E-page 302 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F TABLE 24-2: Base Instr # 48 Assembly Mnemonic MPY MPY MPY 49 50 51 MPY.N MSC MUL MPY.N MSC MUL.SS MUL.SU MUL.US MUL.UU MUL.SU MUL.UU MUL 52 NEG NEG NEG NEG NEG 53 NOP NOP NOPR 54 POP POP POP POP.D POP.S 55 PUSH PUSH PUSH PUSH.D PUSH.S 56 57 PWRSAV RCALL PWRSAV RCALL RCALL 58 REPEAT REPEAT REPEAT 59 60 61 62 63 RESET RETFIE RETLW RETURN RLC RESET RETFIE RETLW RETURN RLC RLC RLC 64 RLNC RLNC RLNC RLNC 65 RRC RRC RRC RRC f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd #lit10,Wn #lit1 Expr Wn #lit14 Wn f Wso Wns f Wdo Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Wm*Wm,Acc,Wx,Wxd,Wy,Wyd, AWB Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,#lit5,Wnd Wb,#lit5,Wnd f Acc f f,WREG Ws,Wd Description Multiply Wm by Wn to Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(Ws) {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(lit5) W3:W2 = f * WREG Negate Accumulator f=f+1 WREG = f + 1 Wd = Ws + 1 No Operation No Operation Pop f from Top-of-Stack (TOS) Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W(nd + 1) Pop Shadow Registers Push f to Top-of-Stack (TOS) Push Wso to Top-of-Stack (TOS) Push W(ns):W(ns + 1) to Top-of-Stack (TOS) Push Shadow Registers Go into Sleep or Idle mode Relative Call Computed Call Repeat Next Instruction lit14 + 1 times Repeat Next Instruction (Wn) + 1 times Software device Reset Return from interrupt Return with literal in Wn Return from Subroutine f = Rotate Left through Carry f WREG = Rotate Left through Carry f Wd = Rotate Left through Carry Ws f = Rotate Left (No Carry) f WREG = Rotate Left (No Carry) f Wd = Rotate Left (No Carry) Ws f = Rotate Right through Carry f WREG = Rotate Right through Carry f Wd = Rotate Right through Carry Ws # of # of Words Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 1 2 2 1 1 1 3 (2) 3 (2) 3 (2) 1 1 1 1 1 1 1 1 1 Status Flags Affected OA,OB,OAB, SA,SB,SAB OA,OB,OAB, SA,SB,SAB None OA,OB,OAB, SA,SB,SAB None None None None None None None OA,OB,OAB, SA,SB,SAB C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z None None None None None All None None None None WDTO,Sleep None None None None None None None None C,N,Z C,N,Z C,N,Z N,Z N,Z N,Z C,N,Z C,N,Z C,N,Z (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 303 dsPIC33F TABLE 24-2: Base Instr # 66 Assembly Mnemonic RRNC RRNC RRNC RRNC 67 SAC SAC SAC.R 68 69 SE SETM SE SETM SETM SETM 70 SFTAC SFTAC SFTAC 71 SL SL SL SL SL SL 72 SUB SUB SUB SUB SUB SUB SUB 73 SUBB SUBB SUBB SUBB SUBB SUBB 74 SUBR SUBR SUBR SUBR SUBR 75 SUBBR SUBBR SUBBR SUBBR SUBBR 76 SWAP SWAP.b SWAP 77 78 79 80 81 82 TBLRDH TBLRDL TBLWTH TBLWTL ULNK XOR TBLRDH TBLRDL TBLWTH TBLWTL ULNK XOR XOR XOR XOR XOR 83 ZE ZE f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Ws,Wnd f f,WREG Ws,Wd Acc,#Slit4,Wdo Acc,#Slit4,Wdo Ws,Wnd f WREG Ws Acc,Wn Acc,#Slit6 f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd Acc f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd Wn Wn Ws,Wd Ws,Wd Ws,Wd Ws,Wd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Description f = Rotate Right (No Carry) f WREG = Rotate Right (No Carry) f Wd = Rotate Right (No Carry) Ws Store Accumulator Store Rounded Accumulator Wnd = sign-extended Ws f = 0xFFFF WREG = 0xFFFF Ws = 0xFFFF Arithmetic Shift Accumulator by (Wn) Arithmetic Shift Accumulator by Slit6 f = Left Shift f WREG = Left Shift f Wd = Left Shift Ws Wnd = Left Shift Wb by Wns Wnd = Left Shift Wb by lit5 Subtract Accumulators f = f - WREG WREG = f - WREG Wn = Wn - lit10 Wd = Wb - Ws Wd = Wb - lit5 f = f - WREG - (C) WREG = f - WREG - (C) Wn = Wn - lit10 - (C) Wd = Wb - Ws - (C) Wd = Wb - lit5 - (C) f = WREG - f WREG = WREG - f Wd = Ws - Wb Wd = lit5 - Wb f = WREG - f - (C) WREG = WREG - f - (C) Wd = Ws - Wb - (C) Wd = lit5 - Wb - (C) Wn = nibble swap Wn Wn = byte swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> to Wd Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer f = f .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR. Wd Wd = Wb .XOR. Ws Wd = Wb .XOR. lit5 Wnd = Zero-extend Ws # of # of Words Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 1 1 1 1 1 1 1 Status Flags Affected N,Z N,Z N,Z None None C,N,Z None None None OA,OB,OAB, SA,SB,SAB OA,OB,OAB, SA,SB,SAB C,N,OV,Z C,N,OV,Z C,N,OV,Z N,Z N,Z OA,OB,OAB, SA,SB,SAB C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z None None None None None None None N,Z N,Z N,Z N,Z N,Z C,Z,N DS70165E-page 304 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 25.0 DEVELOPMENT SUPPORT 25.1 The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB ICE 4000 In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 305 dsPIC33F 25.2 MPASM Assembler 25.5 The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process MPLAB ASM30 Assembler, Linker and Librarian MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 25.6 25.3 MPLAB C18 and MPLAB C30 C Compilers MPLAB SIM Software Simulator The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 family of microcontrollers and the dsPIC30, dsPIC33 and PIC24 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 25.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS70165E-page 306 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 25.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 25.9 MPLAB ICD 2 In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices. The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application. 25.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications. 25.8 MPLAB ICE 4000 High-Performance In-Circuit Emulator The MPLAB ICE 4000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high-end PIC MCUs and dsPIC DSCs. Software control of the MPLAB ICE 4000 In-Circuit Emulator is provided by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 4000 is a premium emulator system, providing the features of MPLAB ICE 2000, but with increased emulation memory and high-speed performance for dsPIC30F and PIC18XXXX devices. Its advanced emulator features include complex triggering and timing, and up to 2 Mb of emulation memory. The MPLAB ICE 4000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 307 dsPIC33F 25.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant. 25.13 Demonstration, Development and Evaluation Boards A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart(R) battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest "Product Selector Guide" (DS00148) for the complete list of demonstration, development and evaluation kits. 25.12 PICkit 2 Development Programmer The PICkitTM 2 Development Programmer is a low-cost programmer with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers. DS70165E-page 308 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 26.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33F electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33F family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(Note 1) Ambient temperature under bias.............................................................................................................. .-40C to +85C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V) Voltage on any digital-only pin with respect to VSS .................................................................................. -0.3V to +5.6V Voltage on VDDCORE with respect to VSS ................................................................................................ 2.25V to 2.75V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin (Note 2)................................................................................................................250 mA Maximum output current sunk by any I/O pin (Note 3) .............................................................................................4 mA Maximum output current sourced by any I/O pin (Note 3) ........................................................................................4 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 2)....................................................................................................200 mA Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 26-2). 3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the VREF+, VREF-, SCLx, SDAx, PGCx and PGDx pins, which are able to sink/source 12 mA. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 309 dsPIC33F 26.1 DC Characteristics OPERATING MIPS VS. VOLTAGE VDD Range (in Volts) 3.0-3.6V Temp Range (in C) -40C to +85C Max MIPS dsPIC33F 40 TABLE 26-1: Characteristic DC5 TABLE 26-2: dsPIC33F THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal chip power dissipation: PINT = VDD x (IDD - IOH) I/O Pin Power Dissipation: I/O = ({VDD - VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation TJ TA -40 -40 -- -- +125 +85 C C PD PINT + PI/O W PDMAX (TJ - TA)/JA W TABLE 26-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ 48.4 52.3 38.7 38.3 Max -- -- -- -- Unit C/W C/W C/W C/W Notes 1 1 1 1 Package Thermal Resistance, 100-pin TQFP (14x14x1 mm) Package Thermal Resistance, 100-pin TQFP (12x12x1 mm) Package Thermal Resistance, 80-pin TQFP (12x12x1 mm) Package Thermal Resistance, 64-pin TQFP (10x10x1 mm) Note 1: JA JA JA JA Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. TABLE 26-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristic Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. Operating Voltage DC10 DC12 DC16 Supply Voltage VDD VDR VPOR RAM Data Retention Voltage(2) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal 3.0 -- -- -- 2.8 VSS 3.6 -- -- V V V DC17 SVDD 0.05 -- -- V/ms 0-3.3V in 0.1s 0-2.5V in 60 ms Note 1: 2: Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. DS70165E-page 310 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F TABLE 26-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. Typical(1) Operating Current (IDD)(2) DC20a DC20b DC21a DC21b DC22a DC22b DC23a DC23b DC24a DC24b Note 1: 2: 27 26 33 32 44 43 60 58 74 72 -- -- -- -- -- -- -- -- -- -- mA mA mA mA mA mA mA mA mA mA +25C +85C +25C +85C +25C +85C +25C +85C +25C +85C 3.3V 3.3V 3.3V 3.3V 3.3V 10 MIPS 16 MIPS 20 MIPS 30 MIPS 40 MIPS Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1 driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD, WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating; however, every peripheral is being clocked (PMD bits are all zeroed). (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 311 dsPIC33F TABLE 26-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. Typical(1) Idle Current (IIDLE): Core OFF Clock ON Base Current(2) DC40a DC40b DC41a DC41b DC42a DC42b DC43a DC43b DC44a DC44b TBD TBD TBD TBD TBD TBD TBD TBD 16.5 16 -- -- -- -- -- -- -- -- -- -- mA mA mA mA mA mA mA mA mA mA +25C +85C +25C +85C +25C +85C +25C +85C +25C +85C 3.3V 3.3V 3.3V 3.3V 3.3V 10 MIPS 16 MIPS 20 MIPS 30 MIPS 40 MIPS Legend: TBD = To Be Determined Note 1: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base IIDLE current is measured with core off, clock on and all modules turned off. Peripheral Module Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to VSS. TABLE 26-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. Typical(1) Power-Down Current (IPD)(2) DC60a DC60b DC61a DC61b 200 TBD TBD TBD -- -- -- -- A A A A +25C +85C +25C +85C 3.3V 3.3V Base Power-Down Current(3,4) Watchdog Timer Current: IWDT(3) Legend: TBD = To Be Determined Note 1: Data in the Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled to VSS. WDT, etc., are all switched off. 3: The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 4: These currents are measured on the device containing the most memory in this family. DS70165E-page 312 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F TABLE 26-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max -- -- -- -- -- -- Doze Ratio 1:2 1:64 1:128 1:2 1:64 1:128 mA 85C mA 25C 3.3V 40 MIPS Units Conditions DC CHARACTERISTICS Typical(1) 42 26 25 41 25 24 Parameter No. DC70a DC70f DC70g DC71a DC71f DC71g Note 1: Data in the Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 313 dsPIC33F TABLE 26-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristic Input Low Voltage I/O pins MCLR OSC1 (XT mode) OSC1 (HS mode) SDAx, SCLx SDAx, SCLx VIH DI20 Input High Voltage I/O pins: with analog functions digital-only MCLR OSC1 (XT mode) OSC1 (HS mode) SDAx, SCLx SDAx, SCLx ICNPU DI30 IIL DI50 DI51 DI55 DI56 Input Leakage I/O ports Analog Input Pins MCLR OSC1 Current(2)(3) -- -- -- -- TBD TBD TBD TBD TBD TBD TBD TBD A A A A VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD, XT and HS modes CNx Pull-up Current 50 250 400 A VDD = 3.3V, VPIN = VSS 0.8 VDD 0.8 VDD 0.8 VDD 0.7 VDD 0.7 VDD 0.7 VDD 0.8 VDD -- -- -- -- -- -- -- VDD 5.5 VDD VDD VDD VDD VDD V V V V V V V SMBus disabled SMBus enabled VSS VSS VSS VSS VSS VSS -- -- -- -- -- -- 0.2 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.2 VDD V V V V V V SMBus disabled SMBus enabled Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. VIL DI10 DI15 DI16 DI17 DI18 DI19 DI25 DI26 DI27 DI28 DI29 Legend: TBD = To Be Determined Note 1: Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS70165E-page 314 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F TABLE 26-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. VOL DO10 DO16 VOH DO20 DO26 Note 1: Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristic Output Low Voltage I/O ports OSC2/CLKO Output High Voltage I/O ports OSC2/CLKO 2.4 2.4 -- -- -- -- V V IOH = -3.0 mA, VDD = 3.3V IOH = -1.3 mA, VDD = 3.3V -- -- -- -- 0.4 0.4 V V IOL = TBD, VDD = 3.3V IOL = TBD, VDD = 3.3V Min Typ(1) Max Units Conditions Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 26-11: DC CHARACTERISTICS: PROGRAM MEMORY DC CHARACTERISTICS Param Symbol No. Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristic Program Flash Memory D130 D131 D132B D133A D134 D135 D136 D137 D138 Note 1: EP VPR VPEW TIW TRETD IDDP TRW TPE TWW Cell Endurance VDD for Read VDD for Self-Timed Write Self-Timed Write Cycle Time Characteristic Retention Supply Current during Programming Row Write Time Page Erase Time Word Write Cycle Time 100 VMIN VMIN -- 20 -- -- -- 20 1000 -- -- 1.5 -- 10 1.6 20 -- -- 3.6 3.6 -- -- -- -- -- 40 E/W -40C to +85C V V ms Year Provided no other specifications are violated mA ms ms s VMIN = Minimum operating voltage VMIN = Minimum operating voltage Min Typ(1) Max Units Conditions Data in "Typ" column is at 3.3V, 25C unless otherwise stated. TABLE 26-12: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40C < TA < +85C (unless otherwise stated) Param No. Symbol CEFC Characteristics External Filter Capacitor Value Min 1 Typ 10 Max -- Units F Comments Capacitor must be low series resistance (< 5 ohms) (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 315 dsPIC33F 26.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC33F AC characteristics and timing parameters. TABLE 26-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Operating voltage VDD range as described in Section 26.0 "Electrical Characteristics". AC CHARACTERISTICS FIGURE 26-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 2 - for OSC2 Load Condition 1 - for all pins except OSC2 VDD/2 RL Pin VSS CL Pin VSS CL RL = 464 CL = 50 pF for all pins except OSC2 15 pF for OSC2 output TABLE 26-14: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol No. DO50 COSC2 Characteristic OSC2/SOSC2 pin Min -- Typ(1) -- Max 15 Units pF Conditions In XT and HS modes when external clock is used to drive OSC1 EC mode In I2CTM mode DO56 DO58 Note 1: CIO CB All I/O pins and OSC2 SCLx, SDAx -- -- -- -- 50 400 pF pF Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. DS70165E-page 316 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F FIGURE 26-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 OS20 OS30 OS25 OS30 OS31 OS31 CLKO OS41 OS40 TABLE 26-15: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param No. OS10 Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristic External CLKI Frequency (External clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency Min 0.8 4 3 3 10 10 12.5 25 0.625 x TOSC -- -- -- Typ(1) -- -- -- -- -- -- -- -- -- -- -- 6 6 Max 64 8 10 10 40 40 33 DC DC -- TBD TBD TBD Units MHz MHz MHz MHz MHz MHz kHz ns ns ns ns ns ns EC EC Conditions EC ECPLL XT XTPLL HS HSPLL SOSC Symb FIN OS20 OS25 OS30 OS31 OS40 OS41 TOSC TCY TosL, TosH TosR, TosF TckR TckF TOSC = 1/FOSC Instruction Cycle Time(2) External Clock in (OSC1) High or Low Time External Clock in (OSC1) Rise or Fall Time CLKO Rise Time(3) CLKO Fall Time(3) Legend: TBD = To Be Determined Note 1: Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices. 3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 317 dsPIC33F TABLE 26-16: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) AC CHARACTERISTICS Param No. OS50 Symbol FPLLI Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristic(1) PLL Voltage Controlled Oscillator (VCO) Input Frequency Range(2) On-Chip VCO System Frequency PLL Start-up Time (Lock Time) CLKO Stability (Jitter) Min 0.8 Typ(2) -- Max 8 Units MHz Conditions ECPLL, HSPLL, XTPLL modes OS51 OS52 OS53 FSYS TLOC DCLK 100 TBD TBD -- 100 1 200 TBD TBD MHz s % Measured over 100 ms period Legend: TBD = To Be Determined Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 26-17: AC CHARACTERISTICS: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for industrial Min Typ Max Units Conditions Internal FRC Accuracy @ 7.3728 MHz(1) F20 FRC TBD TBD -- -- TBD TBD % % +25C -40C TA +85C VDD = 3.0-3.6V VDD = 3.0-3.6V Legend: TBD = To Be Determined Note 1: Frequency calibrated at 25C and 3.3V. TUN bits can be used to compensate for temperature drift. TABLE 26-18: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. Characteristic LPRC @ 32.768 kHz(1) F21 TBD TBD -- -- TBD TBD % % +25C -40C TA +85C VDD = 3.0-3.6V VDD = 3.0-3.6V Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ Max Units Conditions Legend: TBD = To Be Determined Note 1: Change of LPRC frequency as VDD changes. DS70165E-page 318 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F FIGURE 26-3: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Old Value DO31 DO32 Note: Refer to Figure 26-1 for load conditions. New Value TABLE 26-19: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. DO31 DO32 DI35 DI40 Note 1: Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristic Port Output Rise Time Port Output Fall Time INTx Pin High or Low Time (output) CNx High or Low Time (input) Min -- -- 20 2 Typ(1) 10 10 -- -- Max 25 25 -- -- Units ns ns ns TCY Conditions -- -- -- -- Symbol TIOR TIOF TINP TRBP Data in "Typ" column is at 3.3V, 25C unless otherwise stated. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 319 dsPIC33F FIGURE 26-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD MCLR Internal POR SY12 SY10 SY11 PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 26-1 for load conditions. SY20 SY13 SY30 DS70165E-page 320 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F TABLE 26-20: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. SY10 SY11 TMCL TPWRT Characteristic(1) MCLR Pulse Width (low) Power-up Timer Period Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min 2 0.75 1.5 3 6 12 24 48 96 3 -- 1.8 1.9 Oscillator Start-up Timer Period Fail-Safe Clock Monitor Delay -- -- Typ(2) -- 1 2 4 8 16 32 64 128 10 0.8 2.0 2.1 1024 TOSC 500 Max -- 1.25 2.5 5 10 20 40 80 160 30 1.0 2.2 2.3 -- 900 Units s ms Conditions -40C to +85C -40C to +85C User programmable SY12 SY13 SY20 TPOR TIOZ TWDT1 TWDT2 Power-on Reset Delay I/O High-Impedance from MCLR Low or Watchdog Timer Reset Watchdog Timer Time-out Period (No Prescaler) s s ms ms -- s -40C to +85C VDD = 5V, -40C to +85C VDD = 3V, -40C to +85C TOSC = OSC1 period -40C to +85C SY30 SY35 Note 1: 2: 3: TOST TFSCM These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 5V, 25C unless otherwise stated. Characterized by design but not tested. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 321 dsPIC33F FIGURE 26-5: TIMER1, 2, 3, 4, 5, 6, 7, 8 AND 9 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx15 OS60 TMRx Tx11 Tx20 Note: Refer to Figure 26-1 for load conditions. TABLE 26-21: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) AC CHARACTERISTICS Param No. TA10 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Characteristic TxCK High Time Synchronous, no prescaler Synchronous, with prescaler Asynchronous TA11 TTXL TxCK Low Time Synchronous, no prescaler Synchronous, with prescaler Asynchronous TA15 TTXP TxCK Input Period Synchronous, no prescaler Synchronous, with prescaler Asynchronous OS60 Ft1 SOSC1/T1CK Oscillator Input frequency Range (oscillator enabled by setting bit TCS (T1CON<1>)) Min 0.5 TCY + 20 10 10 0.5 TCY + 20 10 10 TCY + 10 Greater of: 20 ns or (TCY + 40)/N 20 DC Typ -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- Units ns ns ns ns ns ns ns -- N = prescale value (1, 8, 64, 256) Must also meet parameter TA15 Conditions Must also meet parameter TA15 Symbol TTXH -- -- -- 50 ns kHz TA20 Note 1: TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment Timer1 is a Type A. 0.5 TCY 1.5 TCY -- DS70165E-page 322 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F TABLE 26-22: TIMER2, TIMER4, TIMER6 AND TIMER8 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param No. TB10 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Characteristic TxCK High Time Synchronous, no prescaler Synchronous, with prescaler TB11 TtxL TxCK Low Time Synchronous, no prescaler Synchronous, with prescaler TB15 TtxP TxCK Input Period Synchronous, no prescaler Synchronous, with prescaler TB20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment Min 0.5 TCY + 20 10 0.5 TCY + 20 10 TCY + 10 Greater of: 20 ns or (TCY + 40)/N 0.5 TCY -- 1.5 TCY -- Typ -- -- -- -- -- Max -- -- -- -- -- Units ns ns ns ns ns N = prescale value (1, 8, 64, 256) Must also meet parameter TB15 Conditions Must also meet parameter TB15 Symbol TtxH TABLE 26-23: TIMER3, TIMER5, TIMER7 AND TIMER9 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param No. TC10 TC11 TC15 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Characteristic TxCK High Time TxCK Low Time Synchronous Synchronous Min 0.5 TCY + 20 0.5 TCY + 20 TCY + 10 Greater of: 20 ns or (TCY + 40)/N 0.5 TCY -- 1.5 TCY -- Typ -- -- -- Max -- -- -- Units ns ns ns Conditions Must also meet parameter TC15 Must also meet parameter TC15 N = prescale value (1, 8, 64, 256) Symbol TtxH TtxL TtxP TxCK Input Period Synchronous, no prescaler Synchronous, with prescaler TC20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 323 dsPIC33F FIGURE 26-6: TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS QEB TQ10 TQ15 POSCNT TQ11 TQ20 TABLE 26-24: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param No. TQ10 TQ11 TQ15 TQ20 Note 1: Characteristic(1) TQCK High Time TQCK Low Time Synchronous, with prescaler Synchronous, with prescaler Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min TCY + 20 TCY + 20 2 * TCY + 40 0.5 TCY Typ Max -- -- -- 1.5 TCY Units ns ns ns -- Conditions Must also meet parameter TQ15 Must also meet parameter TQ15 -- -- Symbol TtQH TtQL TtQP TQCP Input Period Synchronous, with prescaler TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment These parameters are characterized but not tested in manufacturing. DS70165E-page 324 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F FIGURE 26-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC15 Note: Refer to Figure 26-1 for load conditions. IC11 TABLE 26-25: INPUT CAPTURE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. IC10 IC11 IC15 Note 1: Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Characteristic(1) ICx Input Low Time ICx Input High Time ICx Input Period No Prescaler With Prescaler TccH TccP No Prescaler With Prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 (2 TCY + 40)/N Max -- -- -- -- -- Units ns ns ns ns ns N = prescale value (1, 4, 16) Conditions Symbol TccL These parameters are characterized but not tested in manufacturing. FIGURE 26-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure 26-1 for load conditions. TABLE 26-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. OC10 OC11 Note 1: 2: TccF TccR Characteristic(1) OCx Output Fall Time OCx Output Rise Time Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min -- -- Typ(2) -- -- Max -- -- Units ns ns Conditions See parameter D032 See parameter D031 These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 325 dsPIC33F FIGURE 26-9: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx TABLE 26-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. OC15 OC20 Note 1: 2: Characteristic(1) Fault Input to PWM I/O Change Fault Input Pulse Width Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min -- 50 Typ(2) -- -- Max 50 -- Units ns ns Conditions -- -- Symbol TFD TFLT These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. DS70165E-page 326 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F FIGURE 26-10: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS MP30 FLTA/B MP20 PWMx FIGURE 26-11: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure 26-1 for load conditions. TABLE 26-28: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. MP10 MP11 MP20 MP30 Note 1: 2: Characteristic(1) PWM Output Fall Time PWM Output Rise Time Fault Input to PWM I/O Change Minimum Pulse Width Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min -- -- -- 50 Typ(2) -- -- -- -- Max -- -- 50 -- Units ns ns ns ns Conditions See parameter D032 See parameter D031 -- -- Symbol TFPWM TRPWM TFD TFH These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 327 dsPIC33F FIGURE 26-12: QEA/QEB INPUT CHARACTERISTICS TQ36 QEA (input) TQ31 TQ35 TQ30 QEB (input) TQ41 TQ40 TQ31 TQ35 TQ30 QEB Internal TABLE 26-29: QUADRATURE DECODER TIMING REQUIREMENTS AC CHARACTERISTICS Param No. TQ30 TQ31 TQ35 TQ36 TQ40 TQ41 Note 1: 2: 3: Characteristic(1) Quadrature Input Low Time Quadrature Input High Time Quadrature Input Period Quadrature Phase Period Filter Time to Recognize Low, with Digital Filter Filter Time to Recognize High, with Digital Filter Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Typ(2) 6 TCY 6 TCY 12 TCY 3 TCY 3 * N * TCY 3 * N * TCY Max -- -- -- -- -- -- Units ns ns ns ns ns ns Conditions -- -- -- -- N = 1, 2, 4, 16, 32, 64, 128 and 256 (Note 3) N = 1, 2, 4, 16, 32, 64, 128 and 256 (Note 3) Symbol TQUL TQUH TQUIN TQUP TQUFL TQUFH These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. N = Index Channel Digital Filter Clock Divide Select bits. Refer to Section 16. "Quadrature Encoder Interface (QEI)" in the "dsPIC30F Family Reference Manual" (DS70046). DS70165E-page 328 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F FIGURE 26-13: QEA (input) QEI MODULE INDEX PULSE TIMING CHARACTERISTICS QEB (input) Ungated Index TQ51 Index Internal TQ50 TQ55 Position Counter Reset TABLE 26-30: QEI INDEX PULSE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. TQ50 TQ51 TQ55 Note 1: 2: Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Characteristic(1) Filter Time to Recognize Low, with Digital Filter Filter Time to Recognize High, with Digital Filter Index Pulse Recognized to Position Counter Reset (ungated index) Min 3 * N * TCY 3 * N * TCY 3 TCY Max -- -- -- Units ns ns ns Conditions N = 1, 2, 4, 16, 32, 64, 128 and 256 (Note 2) N = 1, 2, 4, 16, 32, 64, 128 and 256 (Note 2) -- Symbol TqIL TqiH Tqidxr These parameters are characterized but not tested in manufacturing. Alignment of index pulses to QEA and QEB is shown for position counter Reset timing only. Shown for forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but index pulse recognition occurs on falling edge. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 329 dsPIC33F FIGURE 26-14: SCKx (CKP = 0) SP11 SCKx (CKP = 1) SP35 SP20 SP21 SP10 SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SP21 SP20 SDOx SP31 SDIx MSb Bit 14 - - - - - -1 SP30 Bit 14 - - - -1 LSb MSb In SP40 SP41 LSb In Note: Refer to Figure 26-1 for load conditions. TABLE 26-31: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param No. SP10 SP11 SP20 SP21 SP30 SP31 SP35 SP40 SP41 Note 1: 2: 3: 4: Characteristic(1) SCKx Output Low Time(3) SCKx Output High Time(3) SCKx Output Fall Time(4) SCKx Output Rise Time(4) SDOx Data Output Fall Time(4) SDOx Data Output Rise Time(4) SDOx Data Output Valid after SCKx Edge Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min TCY/2 TCY/2 -- -- -- -- -- 20 20 Typ(2) -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 30 -- -- Units ns ns ns ns ns ns ns ns ns Conditions -- -- See parameter D032 See parameter D031 See parameter D032 See parameter D031 -- -- -- Symbol TscL TscH TscF TscR TdoF TdoR TscH2doV, TscL2doV TdiV2scH, TdiV2scL TscH2diL, TscL2diL These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. DS70165E-page 330 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F FIGURE 26-15: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SP10 SP21 SP20 SCKX (CKP = 1) SP35 SP20 SP21 SDOX MSb SP40 Bit 14 - - - - - -1 SP30,SP31 Bit 14 - - - -1 LSb SDIX MSb In SP41 LSb In Note: Refer to Figure 26-1 for load conditions. TABLE 26-32: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param No. SP10 SP11 SP20 SP21 SP30 SP31 SP35 SP36 SP40 SP41 Note 1: 2: 3: 4: Characteristic(1) SCKx Output Low Time(3) SCKx Output High Time(3) SCKx Output Fall Time(4) SCKx Output Rise Time(4) SDOx Data Output Fall Time(4) SDOx Data Output Rise Time(4) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min TCY/2 TCY/2 -- -- -- -- -- 30 20 20 Typ(2) -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- -- -- Units ns ns ns ns ns ns ns ns ns ns Conditions -- -- See parameter D032 See parameter D031 See parameter D032 See parameter D031 -- -- -- -- Symbol TscL TscH TscF TscR TdoF TdoR TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge TdoV2sc, SDOx Data Output Setup to TdoV2scL First SCKx Edge TdiV2scH, Setup Time of SDIx Data TdiV2scL Input to SCKx Edge TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 331 dsPIC33F FIGURE 26-16: SSX SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP52 SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SCKX (CKP = 1) SP35 SDOX MSb SP72 SP73 Bit 14 - - - - - -1 SP30,SP31 LSb SP51 LSb In SDIX MSb In SP41 SP40 Bit 14 - - - -1 Note: Refer to Figure 26-1 for load conditions. TABLE 26-33: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param No. SP70 SP71 SP72 SP73 SP30 SP31 SP35 Characteristic(1) SCKx Input Low Time SCKx Input High Time SCKx Input Fall Time(3) SCKx Input Rise Time(3) SDOx Data Output Fall Time (3) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min 30 30 -- -- -- -- -- Typ(2) -- -- 10 10 -- -- -- Max -- -- 25 25 -- -- 30 Units ns ns ns ns ns ns ns Conditions -- -- -- -- See parameter D032 See parameter D031 -- Symbol TscL TscH TscF TscR TdoF TdoR SDOx Data Output Rise Time(3) TscH2doV SDOx Data Output Valid after , SCKx Edge TscL2doV TdiV2scH, Setup Time of SDIx Data Input TdiV2scL to SCKx Edge TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge SP40 SP41 SP50 SP51 Note 1: 2: 3: 20 20 120 10 -- -- -- -- -- -- -- 50 ns ns ns ns -- -- -- -- TssL2scH, SSx to SCKx or SCKx Input TssL2scL TssH2doZ SSx to SDOx Output High-Impedance(3) These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Assumes 50 pF load on all SPIx pins. DS70165E-page 332 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F TABLE 26-33: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS (CONTINUED) AC CHARACTERISTICS Param No. SP52 Note 1: 2: 3: Characteristic(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min 1.5 TCY +40 Typ(2) -- Max -- Units ns Conditions -- Symbol TscH2ssH SSx after SCKx Edge TscL2ssH These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Assumes 50 pF load on all SPIx pins. FIGURE 26-17: SSx SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SP50 SCKx (CKP = 0) SP71 SCKx (CKP = 1) SP35 SP52 SDOx MSb Bit 14 - - - - - -1 SP30,SP31 SDIx SDI MSb In SP41 SP40 Note: Refer to Figure 26-1 for load conditions. Bit 14 - - - -1 LSb In SP72 LSb SP70 SP73 SP52 SP72 SP73 SP51 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 333 dsPIC33F TABLE 26-34: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param No. SP70 SP71 SP72 SP73 SP30 SP31 SP35 Characteristic(1) SCKx Input Low Time SCKx Input High Time SCKx Input Fall Time (3) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min 30 30 -- -- (3) Symbol TscL TscH TscF TscR TdoF TdoR Typ(2) -- -- 10 10 -- -- -- Max -- -- 25 25 -- -- 30 Units ns ns ns ns ns ns ns Conditions -- -- -- -- See parameter D032 See parameter D031 -- SCKx Input Rise Time(3) SDOx Data Output Fall Time SDOx Data Output Rise Time(3) -- -- -- TscH2doV SDOx Data Output Valid after , SCKx Edge TscL2doV TdiV2scH, Setup Time of SDIx Data Input TdiV2scL to SCKx Edge TscH2diL, Hold Time of SDIx Data Input TscL2diL to SCKx Edge TssL2scH, SSx to SCKx or SCKx TssL2scL Input TssH2doZ SSx to SDOX Output High-Impedance(4) TscH2ssH SSx after SCKx Edge TscL2ssH TssL2doV SDOx Data Output Valid after SSx Edge SP40 SP41 SP50 SP51 SP52 SP60 Note 1: 2: 3: 4: 20 20 120 10 1.5 TCY + 40 -- -- -- -- -- -- -- -- -- -- 50 -- 50 ns ns ns ns ns ns -- -- -- -- -- -- These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. DS70165E-page 334 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F FIGURE 26-18: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM30 IM33 IM34 SDAx Start Condition Note: Refer to Figure 26-1 for load conditions. Stop Condition FIGURE 26-19: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM10 IM21 SCLx IM11 IM10 IM26 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 26-1 for load conditions. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 335 dsPIC33F TABLE 26-35: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) AC CHARACTERISTICS Param Symbol No. IM10 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Characteristic Min(1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) -- 20 + 0.1 CB -- -- 20 + 0.1 CB -- 250 100 TBD 0 0 TBD TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) -- -- -- 4.7 1.3 TBD -- Max -- -- -- -- -- -- 300 300 100 1000 300 300 -- -- -- -- 0.9 -- -- -- -- -- -- -- -- -- -- -- -- -- 3500 1000 -- -- -- -- 400 Units s s s s s s ns ns ns ns ns ns ns ns ns ns s ns s s s s s s s s s ns ns ns ns ns ns s s s pF -- -- -- Time the bus must be free before a new transmission can start -- Only relevant for Repeated Start condition After this period the first clock pulse is generated -- -- -- CB is specified to be from 10 to 400 pF Conditions -- -- -- -- -- -- CB is specified to be from 10 to 400 pF TLO:SCL Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode(2) IM11 THI:SCL Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode (2) IM20 TF:SCL SDAx and SCLx 100 kHz mode Fall Time 400 kHz mode 1 MHz mode(2) SDAx and SCLx 100 kHz mode Rise Time 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) IM21 TR:SCL IM25 TSU:DAT Data Input Setup Time IM26 THD:DAT Data Input Hold Time IM30 TSU:STA Start Condition Setup Time IM31 THD:STA Start Condition Hold Time IM33 TSU:STO Stop Condition Setup Time IM34 THD:STO Stop Condition Hold Time IM40 TAA:SCL Output Valid From Clock IM45 TBF:SDA Bus Free Time IM50 CB Bus Capacitive Loading Legend: TBD = To Be Determined Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 21. "Inter-Integrated Circuit (I2CTM)" in the "dsPIC30F Family Reference Manual" (DS70046). 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). DS70165E-page 336 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F FIGURE 26-20: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS30 IS33 IS34 SDAx Start Condition Stop Condition FIGURE 26-21: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS10 IS30 IS26 IS21 SCLx IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 337 dsPIC33F TABLE 26-36: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) AC CHARACTERISTICS Param No. IS10 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Characteristic Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode(1) IS11 THI:SCL Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode(1) IS20 TF:SCL SDAx and SCLx Fall Time 100 kHz mode 400 kHz mode 1 MHz IS21 TR:SCL SDAx and SCLx Rise Time mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) IS25 TSU:DAT Data Input Setup Time 100 kHz mode 400 kHz mode 1 MHz IS26 THD:DAT Data Input Hold Time mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) IS30 TSU:STA Start Condition Setup Time 100 kHz mode 400 kHz mode 1 MHz IS31 THD:STA Start Condition Hold Time mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) IS33 TSU:STO Stop Condition Setup Time 100 kHz mode 400 kHz mode 1 MHz IS34 THD:STO Stop Condition Hold Time mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) IS40 TAA:SCL Output Valid From Clock 100 kHz mode 400 kHz mode 1 MHz IS45 TBF:SDA Bus Free Time mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) IS50 Note 1: CB Bus Capacitive Loading Min 4.7 1.3 0.5 4.0 0.6 0.5 -- 20 + 0.1 CB -- -- 20 + 0.1 CB -- 250 100 100 0 0 0 4.7 0.6 0.25 4.0 0.6 0.25 4.7 0.6 0.6 4000 600 250 0 0 0 4.7 1.3 0.5 -- 3500 1000 350 -- -- -- 400 Max -- -- -- -- -- -- 300 300 100 1000 300 300 -- -- -- -- 0.9 0.3 -- -- -- -- -- -- -- -- -- -- -- Units s s s s s s ns ns ns ns ns ns ns ns ns ns s s s s s s s s s s s ns ns ns ns ns ns s s s pF Time the bus must be free before a new transmission can start -- -- -- -- After this period, the first clock pulse is generated Only relevant for Repeated Start condition -- -- CB is specified to be from 10 to 400 pF Conditions Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz -- Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz -- CB is specified to be from 10 to 400 pF Symbol TLO:SCL Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). DS70165E-page 338 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F FIGURE 26-22: DCI MODULE (MULTI-CHANNEL, I2S MODES) TIMING CHARACTERISTICS CSCK (SCKE = 0) CS11 CSCK (SCKE = 1) CS20 COFS CS55 CS56 CS35 CS51 CSDO High-Z CS50 MSb CS30 CSDI MSb In CS40 CS41 CS31 LSb In LSb 70 High-Z CS21 CS10 CS21 CS20 Note: Refer to Figure 26-1 for load conditions. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 339 dsPIC33F TABLE 26-37: DCI MODULE (MULTI-CHANNEL, I2S MODES) TIMING REQUIREMENTS AC CHARACTERISTICS Param No. CS10 Characteristic(1) CSCK Input Low Time (CSCK pin is an input) CSCK Output Low Time(3) (CSCK pin is an output) CS11 TCSCKH CSCK Input High Time (CSCK pin is an input) CSCK Output High Time(3) (CSCK pin is an output) CS20 CS21 CS30 CS31 CS35 CS36 CS40 TCSCKF TCSCKR TCSDOF TCSDOR TDV TDIV TCSDI CSCK Output Fall Time(4) (CSCK pin is an output) CSCK Output Rise Time(4) (CSCK pin is an output) CSDO Data Output Fall Time(4) CSDO Data Output Rise Time(4) Clock Edge to CSDO Data Valid Clock Edge to CSDO Tri-Stated Setup Time of CSDI Data Input to CSCK Edge (CSCK pin is input or output) Hold Time of CSDI Data Input to CSCK Edge (CSCK pin is input or output) COFS Fall Time (COFS pin is output) COFS Rise Time (COFS pin is output) Setup Time of COFS Data Input to CSCK Edge (COFS pin is input) Hold Time of COFS Data Input to CSCK Edge (COFS pin is input) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min TCY/2 + 20 30 TCY/2 + 20 30 -- -- -- -- -- 10 20 Typ(2) -- -- -- -- 10 10 10 10 -- -- -- Max -- -- -- -- 25 25 25 25 10 20 -- Units ns ns ns ns ns ns ns ns ns ns ns Conditions -- -- -- -- -- -- -- -- -- -- -- Symbol TCSCKL CS41 THCSDI 20 -- -- ns -- CS50 CS51 CS55 TCOFSF TCOFSR TSCOFS -- -- 20 10 10 -- 25 25 -- ns ns ns Note 1 Note 1 -- CS56 Note 1: 2: 3: 4: THCOFS 20 -- -- ns -- These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all DCI pins. DS70165E-page 340 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F FIGURE 26-23: BIT_CLK (CSCK) CS61 CS60 CS62 CS21 CS20 DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS CS71 CS72 CS70 SYNC (COFS) CS76 CS80 CS75 SDOx (CSDO) LSb MSb LSb CS76 CS75 SDIx (CSDI) MSb In CS65 CS66 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 341 dsPIC33F TABLE 26-38: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS AC CHARACTERISTICS Param No. CS60 CS61 CS62 CS65 CS66 CS70 CS71 CS72 CS75 CS76 CS77 CS78 CS80 Legend: Note 1: 2: 3: Characteristic(1,2) BIT_CLK Low Time BIT_CLK High Time BIT_CLK Period Input Setup Time to Falling Edge of BIT_CLK Input Hold Time from Falling Edge of BIT_CLK SYNC Data Output Low Time SYNC Data Output High Time SYNC Data Output Period Rise Time, SYNC, SDATA_OUT Fall Time, SYNC, SDATA_OUT Rise Time, SYNC, SDATA_OUT Fall Time, SYNC, SDATA_OUT Output Valid Delay from Rising Edge of BIT_CLK Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min 36 36 -- -- -- -- -- -- -- -- -- -- -- Typ(3) 40.7 40.7 81.4 -- -- 19.5 1.3 20.8 10 10 TBD TBD -- Max 45 45 -- 10 10 -- -- -- 25 25 TBD TBD 15 Units ns ns ns ns ns s s s ns ns ns ns ns Note 1 Note 1 Note 1 CLOAD = 50 pF, VDD = 5V CLOAD = 50 pF, VDD = 5V CLOAD = 50 pF, VDD = 3V CLOAD = 50 pF, VDD = 3V -- Conditions -- -- Bit clock is input -- -- Symbol TBCLKL TBCLKH TBCLK TSACL THACL TSYNCLO TSYNCHI TSYNC TRACL TFACL TRACL TFACL TOVDACL TBD = To Be Determined These parameters are characterized but not tested in manufacturing. These values assume BIT_CLK frequency is 12.288 MHz. Data in "Typ" column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. DS70165E-page 342 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F FIGURE 26-24: CAN MODULE I/O TIMING CHARACTERISTICS CiTx Pin (output) Old Value CA10 CA11 New Value CiRx Pin (input) CA20 TABLE 26-39: CAN MODULE I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. CA10 CA11 CA20 Note 1: 2: Characteristic(1) Port Output Fall Time Port Output Rise Time Pulse Width to Trigger CAN Wake-up Filter Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min -- -- 500 Typ(2) -- -- Max -- -- Units ns ns ns Conditions See parameter D032 See parameter D031 -- Symbol TioF TioR Tcwf These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 26-40: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param No. Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Characteristic Min. Typ Max. Units Conditions Symbol Device Supply AD01 AVDD Module VDD Supply Greater of VDD - 0.3 or 3.0 VSS - 0.3 AVSS + 1.7 -- Lesser of VDD + 0.3 or 3.6 VSS + 0.3 AVDD V -- AD02 AD05 AVSS VREFH Module VSS Supply Reference Voltage High -- -- V V -- -- Reference Inputs Legend: TBD = To Be Determined Note 1: The ADC conversion result never decreases with an increase in the input voltage, and has no missing codes. 2: Measurements taken with external VREF+ and VREF- used as the ADC voltage reference. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 343 dsPIC33F TABLE 26-40: ADC MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS Param No. AD06 AD07 AD08 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Characteristic Reference Voltage Low Absolute Reference Voltage Current Drain Min. AVSS AVSS - 0.3 -- Typ -- -- 150 .001 Max. AVDD - 1.7 AVDD + 0.3 200 1 VREFH AVDD + 0.3 0.001 0.610 Units V V A A V V A Conditions -- -- ADC operating ADC off See Note -- VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V Source Impedance = 2.5 K VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V Source Impedance = 2.5 K 10-bit 12-bit Symbol VREFL VREF IREF Analog Input AD10 AD11 AD12 VINH-VINL Full-Scale Input Span VIN -- Absolute Input Voltage Leakage Current VREFL AVSS - 0.3 -- AD13 -- Leakage Current -- 0.001 0.610 A AD17 RIN Recommended Impedance -- -- 1K of Analog Voltage Source 2.5K ADC Accuracy (12-bit Mode) Resolution Integral Nonlinearity (2) bits AD20a Nr AD21a INL AD22a DNL AD23a GERR AD24a EOFF AD25a -- AD30a THD AD31a SINAD AD32a SFDR AD33a FNYQ AD34a ENOB AD20b Nr AD21b INL 12 data bits -- -- TBD TBD -- -- -- -- -- -- -- -- TBD TBD -- TBD TBD TBD -- TBD 10 data bits -- TBD <2 <2 <1 3 2 -- -- -- -- 250 -- LSb LSb LSb LSb -- dB dB dB kHz bits bits LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V Guaranteed -- -- -- -- -- Differential Nonlinearity(2) Gain Error(2) Offset Error(2) Monotonicity(1) Total Harmonic Distortion Signal to Noise and Distortion Spurious Free Dynamic Range Input Signal Bandwidth Effective Number of Bits Resolution Integral Nonlinearity Dynamic Performance (12-bit Mode) ADC Accuracy (10-bit Mode) VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V Legend: TBD = To Be Determined Note 1: The ADC conversion result never decreases with an increase in the input voltage, and has no missing codes. 2: Measurements taken with external VREF+ and VREF- used as the ADC voltage reference. DS70165E-page 344 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F TABLE 26-40: ADC MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS Param No. Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Characteristic Differential Nonlinearity Gain Error Offset Error Monotonicity(1) Total Harmonic Distortion Signal to Noise and Distortion Spurious Free Dynamic Range Input Signal Bandwidth Effective Number of Bits Min. -- TBD TBD -- -- -- -- -- TBD Typ TBD TBD TBD -- TBD TBD TBD -- TBD Max. <1 3 2 -- -- -- -- 550 -- Units LSb LSb LSb -- dB dB dB kHz bits Conditions VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V Guaranteed -- -- -- -- -- Symbol AD22b DNL AD23b GERR AD24b EOFF AD25b -- AD30b THD AD31b SINAD AD32b SFDR AD33b FNYQ AD34b ENOB Dynamic Performance (10-bit Mode) Legend: TBD = To Be Determined Note 1: The ADC conversion result never decreases with an increase in the input voltage, and has no missing codes. 2: Measurements taken with external VREF+ and VREF- used as the ADC voltage reference. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 345 dsPIC33F FIGURE 26-25: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 TSAMP CONV ADxIF Buffer(0) Buffer(1) AD55 AD55 Clear SAMP 1 2 3 4 5 6 7 8 5 6 7 8 1 - Software sets ADxCON. SAMP to start sampling. 2 - Sampling starts after discharge period. TSAMP is described in Section 17 in the "dsPIC30F Family Reference Manual". 3 - Software clears ADxCON. SAMP to start conversion. 4 - Sampling ends, conversion sequence starts. 5 - Convert bit 9. 6 - Convert bit 8. 7 - Convert bit 0. 8 - One TAD for end of conversion. DS70165E-page 346 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F FIGURE 26-26: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Execution SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc Set ADON TSAMP AD55 CONV ADxIF Buffer(0) Buffer(1) AD55 TSAMP TCONV 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 - Software sets ADxCON. ADON to start AD operation. 2 - Sampling starts after discharge period. TSAMP is described in the "dsPIC30F Family Reference Manual", Section 17. 3 - Convert bit 9. 4 - Convert bit 8. 5 - Convert bit 0. 6 - One TAD for end of conversion. 7 - Begin conversion of next channel. 8 - Sample for time specified by SAMC<4:0>. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 347 dsPIC33F TABLE 26-41: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Characteristic Min. Typ(1) Max. Units Conditions Clock Parameters AD50 AD51 AD55 AD56 AD57 AD60 TAD tRC tCONV FCNV TSAMP tPCS ADC Clock Period ADC Internal RC Oscillator Period Conversion Time Throughput Rate Sample Time Conversion Start from Sample Trigger(3) Sample Start from Setting Sample (SAMP) bit Conversion Completion to Sample Start (ASAM = 1)(3) Time to Stabilize Analog Stage from ADC Off to ADC On(3) 70 -- -- -- -- -- -- 250 12 TAD -- 1 TAD 1.0 TAD -- -- -- 1.1 -- -- ns ns -- Msps -- -- Auto-Convert Trigger (SSRC<2:0> = 111) not selected -- -- -- TCY = 70ns, ADxCON3 in default state Conversion Rate Timing Parameters AD61 AD62 AD63 Note 1: 2: 3: tPSS tCSS tDPU 0.5 TAD -- -- -- 0.5 TAD 20 1.5 TAD -- -- -- -- s These parameters are characterized but not tested in manufacturing. Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. Characterized by design but not tested. DS70165E-page 348 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F FIGURE 26-27: ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution SAMP ch0_dischrg ch0_samp eoc AD61 AD60 TSAMP CONV ADxIF Buffer(0) AD55 Set SAMP Clear SAMP 1 2 3 4 5 6 7 8 9 1 - Software sets ADxCON. SAMP to start sampling. 2 - Sampling starts after discharge period. TSAMP is described in the "dsPIC30F Family Reference Manual", Section 17. 3 - Software clears ADxCON. SAMP to start conversion. 4 - Sampling ends, conversion sequence starts. 5 - Convert bit 11. 6 - Convert bit 10. 7 - Convert bit 1. 8 - Convert bit 0. 9 - One TAD for end of conversion. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 349 dsPIC33F TABLE 26-42: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS) AC CHARACTERISTICS Param No. Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Characteristic Min. Typ Max. Units Conditions Symbol Clock Parameters AD50 TAD ADC Clock Period 133 -- -- ns TCY = 133ns, ADxCON3 in default state AD51 tRC ADC Internal RC Oscillator Period Conversion Time Throughput Rate Sample Time Conversion Start from Sample Trigger Sample Start from Setting Sample (SAMP) bit Conversion Completion to Sample Start (ASAM = 1) Time to Stabilize Analog Stage from ADC Off to ADC On -- 250 -- ns Conversion Rate AD55 AD56 AD57 AD60 AD61 AD62 AD63 tCONV FCNV TSAMP tPCS tPSS tCSS tDPU -- -- -- -- 0.5 TAD -- -- 14 TAD -- 1 TAD 1.0 TAD -- -- 20 500 -- -- 1.5 TAD -- -- ns ksps ns ns ns ns s -- -- -- -- Timing Parameters Legend: TBD = To Be Determined Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. DS70165E-page 350 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 27.0 27.1 PACKAGING INFORMATION Package Marking Information 64-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 80-Lead TQFP (12x12x1 mm) dsPIC33FJ 256GP706 -I/PT e3 0710017 Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN dsPIC33FJ128 GP708-I/PT e3 0710017 100-Lead TQFP (12x12x1 mm) Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN dsPIC33FJ256 GP710-I/PT e3 0710017 100-Lead TQFP (14x14x1mm) Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN dsPIC33FJ256 GP710-I/PF e3 0710017 Legend: XX...X Y YY WW NNN e3 * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 351 dsPIC33F 27.2 Package Details The following sections give the technical details of the packages. 64-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 123 NOTE 2 A c A2 L A1 L1 Units Dimension Limits Number of Leads Lead Pitch Overall Height Molded Package Thickness Standoff Foot Length Footprint Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 L L1 E D E1 D1 c b 0.09 0.17 11 11 0 - 0.95 0.05 0.45 MIN MILLIMETERS NOM 64 0.50 BSC - 1.00 - 0.60 1.00 REF 3.5 12.00 BSC 12.00 BSC 10.00 BSC 10.00 BSC - 0.22 12 12 0.20 0.27 13 13 7 1.20 1.05 0.15 0.75 MAX Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-085B DS70165E-page 352 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 80-Lead Plastic Thin Quad Flatpack (PT) - 12x12x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 b N 12 3 NOTE 2 NOTE 1 c A L A1 A2 L1 Units Dimension Limits Number of Leads Lead Pitch Overall Height Molded Package Thickness Standoff Foot Length Footprint Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 L L1 E D E1 D1 c b 0.09 0.17 11 11 0 - 0.95 0.05 0.45 MIN MILLIMETERS NOM 80 0.50 BSC - 1.00 - 0.60 1.00 REF 3.5 14.00 BSC 14.00 BSC 12.00 BSC 12.00 BSC - 0.22 12 12 0.20 0.27 13 13 7 1.20 1.05 0.15 0.75 MAX Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-092B (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 353 dsPIC33F 100-Lead Plastic Thin Quad Flatpack (PT) - 12x12x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 e E E1 b N 1 23 NOTE 2 A L Units Dimension Limits Number of Leads Lead Pitch Overall Height Molded Package Thickness Standoff Foot Length Footprint Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 L L1 E D E1 D1 c b 0.09 0.13 11 11 0 - 0.95 0.05 0.45 MIN NOTE 1 c A1 L1 MILLIMETERS NOM 100 0.40 BSC - 1.00 - 0.60 1.00 REF 3.5 14.00 BSC 14.00 BSC 12.00 BSC 12.00 BSC - 0.18 12 12 0.20 0.23 13 13 7 1.20 1.05 0.15 0.75 MAX A2 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-100B DS70165E-page 354 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F 100-Lead Plastic Thin Quad Flatpack (PF) - 14x14x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 e E1 E b N NOTE 1 1 23 NOTE 2 A c L A1 A2 L1 Units Dimension Limits Number of Leads Lead Pitch Overall Height Molded Package Thickness Standoff Foot Length Footprint Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 L L1 E D E1 D1 c b 0.09 0.17 11 11 0 - 0.95 0.05 0.45 MIN MILLIMETERS NOM 100 0.50 BSC - 1.00 - 0.60 1.00 REF 3.5 16.00 BSC 16.00 BSC 14.00 BSC 14.00 BSC - 0.22 12 12 0.20 0.27 13 13 7 1.20 1.05 0.15 0.75 MAX Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-110B (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 355 dsPIC33F NOTES: DS70165E-page 356 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F APPENDIX A: REVISION HISTORY Revision A (October 2005) * Initial release of this document Revision B (February 2006) * * * * Updated Register descriptions and memory maps Revised Oscillator section Updated ADC characteristics Updated Thermal Packaging characteristics * Corrected mislabeled I2COV bit in I2CxCON register (see Register 18-1) * Removed AD26a, AD27a, AD28a, AD26b, AD27b, AD28b from Table 26-40 (ADC Module). Revision E (January 2007) * This revision includes updates to the packaging diagrams. Revision C (March 2006) * Information related to prototype samples removed * Flash memory characteristics updated * Incorrect references to SPI FIFO buffers removed. These buffers are not supported by the dsPIC33F family. * DC Characteristics updated * Device Configuration registers updated Revision D (July 2006) * Added FBS and FSS Device Configuration registers (see Table 23-1) and corresponding bit field descriptions (see Table 23-2). These added registers replaced the former RESERVED1 and RESERVED2 registers. * Added INTTREG Interrupt Control and Status register. (See Section 6.3 "Interrupt Control and Status Registers". See also Register 6-33.) * Added Core Registers BSRAM and SSRAM (see Section 3.2.8 "Data Ram Protection Feature") * Clarified Fail-Safe Clock Monitor operation (see Section 8.3 "Fail-Safe Clock Monitor (FSCM)") * Updated COSC<2:0> and NOSC<2:0> bit configurations in OSCCON register (see Register 8-1) * Updated CLKDIV register bit configurations (see Register 8-2) * Added Word Write Cycle Time parameter (TWW) to Program Flash Memory (see Table 26-11) * Noted exceptions to Absolute Maximum Ratings on I/O pin output current (see Section 26.0 "Electrical Characteristics") * Added ADC2 Event Trigger for Timer4/5 (Section 12.0 "Timer2/3, Timer4/5, Timer6/7 and Timer8/9") * Corrected mislabeled 2COV bit in I2CxSTAT register (see Table 18-1) * Added QEI Register descriptions (see Register 16-1 and Register 16-2) * Corrected mislabeled PMOD<4:1> field in PWMCON register (see Register 15-5) * Corrected mislabeled UPDN_SRC bit in QEICON register (see Register 16-1) (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 357 dsPIC33F NOTES: DS70165E-page 358 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F INDEX A A/D Converter ................................................................... 275 DMA .......................................................................... 275 Initialization ............................................................... 275 Key Features............................................................. 275 AC Characteristics ............................................................ 316 Internal RC Accuracy ................................................ 318 Load Conditions ........................................................ 316 AC-Link Mode Operation .................................................. 268 16-bit Mode ............................................................... 268 20-bit Mode ............................................................... 269 ADC Module ADC11 Register Map .................................................. 55 ADC2 Register Map .................................................... 55 Alternate Vector Table (AIVT) ............................................. 87 Arithmetic Logic Unit (ALU)................................................. 33 Assembler MPASM Assembler................................................... 306 Automatic Clock Stretch.................................................... 215 Receive Mode ........................................................... 215 Transmit Mode .......................................................... 215 Port Write/Read ........................................................ 160 PWRSAV Instruction Syntax .................................... 157 Code Protection ........................................................ 289, 295 Configuration Bits ............................................................. 289 Description (Table) ................................................... 290 Configuration Register Map .............................................. 289 Configuring Analog Port Pins............................................ 160 CPU Control Register.......................................................... 30 CPU Clocking System ...................................................... 150 Options ..................................................................... 150 Selection................................................................... 150 Customer Change Notification Service............................. 365 Customer Notification Service .......................................... 365 Customer Support............................................................. 365 D Data Accumulators and Adder/Subtractor .......................... 35 Data Space Write Saturation ...................................... 37 Overflow and Saturation ............................................. 35 Round Logic ............................................................... 36 Write Back .................................................................. 36 Data Address Space........................................................... 41 Alignment.................................................................... 41 Memory Map for dsPIC33F Devices with 16 KBs RAM ....................................................... 43 Memory Map for dsPIC33F Devices with 30 KBs RAM ....................................................... 44 Memory Map for dsPIC33F Devices with 8 KBs RAM ......................................................... 42 Near Data Space ........................................................ 41 Software Stack ........................................................... 67 Width .......................................................................... 41 Data Converter Interface (DCI) Module ............................ 261 DC Characteristics............................................................ 310 I/O Pin Input Specifications ...................................... 314 I/O Pin Output Specifications.................................... 315 Idle Current (IDOZE) .................................................. 313 Idle Current (IIDLE) .................................................... 312 Operating Current (IDD) ............................................ 311 Power-Down Current (IPD)........................................ 312 Program Memory...................................................... 315 Temperature and Voltage Specifications.................. 310 DCI Bit Clock Generator .................................................. 265 Buffer Alignment with Data Frames.......................... 267 Buffer Control ........................................................... 261 Buffer Data Alignment .............................................. 261 Buffer Length Control ............................................... 267 CSDO Mode Bit ........................................................ 268 Data Justification Control Bit .................................... 266 Device Frequencies for Common Codec CSCK Frequencies (Table) .............................. 265 Digital Loopback Mode ............................................. 268 Frame Sync Generator ............................................. 263 Frame Sync Mode Control Bits................................. 263 Interrupts .................................................................. 268 Introduction............................................................... 261 Master Frame Sync Operation ................................. 263 Module Enable.......................................................... 263 Operation.................................................................. 263 Operation During CPU Idle Mode............................. 268 Operation During CPU Sleep Mode ......................... 268 Receive Slot Enable Bits .......................................... 266 B Barrel Shifter ....................................................................... 37 Bit-Reversed Addressing .................................................... 70 Example ...................................................................... 71 Implementation ........................................................... 70 Sequence Table (16-Entry)......................................... 71 Block Diagrams 16-bit Timer1 Module ................................................ 161 A/D Module ....................................................... 276, 277 Connections for On-Chip Voltage Regulator............. 293 DCI Module ............................................................... 261 Device Clock ..................................................... 149, 151 DSP Engine ................................................................ 34 dsPIC33F .................................................................... 24 dsPIC33F CPU Core................................................... 28 ECAN Module ........................................................... 231 Input Capture ............................................................ 169 Output Compare ....................................................... 173 PLL............................................................................ 151 PWM Module ............................................................ 176 Quadrature Encoder Interface .................................. 197 Reset System.............................................................. 83 Shared Port Structure ............................................... 159 SPI ............................................................................ 206 Timer2 (16-bit) .......................................................... 165 Timer2/3 (32-bit) ....................................................... 164 UART ........................................................................ 223 Watchdog Timer (WDT) ............................................ 294 C C Compilers MPLAB C18 .............................................................. 306 MPLAB C30 .............................................................. 306 Clock Switching................................................................. 156 Enabling .................................................................... 156 Sequence.................................................................. 156 Code Examples DMA Sample Initialization Method ............................ 139 Erasing a Program Memory Page............................... 80 Initiating a Programming Sequence............................ 81 Loading Write Buffers ................................................. 81 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 359 dsPIC33F Receive Status Bits ................................................... 267 Sample Clock Edge Control Bit................................. 266 Slave Frame Sync Operation .................................... 264 Slot Enable Bits Operation with Frame Sync ............ 266 Slot Status Bits.......................................................... 268 Synchronous Data Transfers .................................... 266 Transmit Slot Enable Bits.......................................... 266 Transmit Status Bits .................................................. 267 Transmit/Receive Shift Register ............................... 261 Underflow Mode Control Bit ...................................... 268 Word Size Selection Bits........................................... 263 DCI I/O Pins ...................................................................... 261 COFS ........................................................................ 261 CSCK ........................................................................ 261 CSDI ......................................................................... 261 CSDO........................................................................ 261 DCI Module Register Map............................................................... 64 Development Support ....................................................... 305 DMA Interrupts and Traps.................................................. 138 Request Source Selection ........................................ 138 DMA Module DMA Register Map...................................................... 56 DMAC Operating Modes ................................................... 136 Addressing ................................................................ 137 Byte or Word Transfer............................................... 137 Continuous or One-Shot ........................................... 138 Manual Transfer ........................................................ 138 Null Data Peripheral Write ........................................ 137 Ping-Pong ................................................................. 138 Transfer Direction ..................................................... 137 DMAC Registers ............................................................... 136 DMAxCNT ................................................................. 136 DMAxCON ................................................................ 136 DMAxPAD ................................................................. 136 DMAxREQ ................................................................ 136 DMAxSTA ................................................................. 136 DMAxSTB ................................................................. 136 DSP Engine......................................................................... 33 Multiplier...................................................................... 35 PWM Resolution ....................................................... 178 Relationship Between Device and SPI Clock Speed ..................................................... 208 Serial Clock Rate ...................................................... 213 Time Quantum for Clock Generation ........................ 237 UART Baud Rate with BRGH = 0 ............................. 224 UART Baud Rate with BRGH = 1 ............................. 224 Errata .................................................................................. 21 F Flash Program Memory ...................................................... 77 Control Registers ........................................................ 78 Operations .................................................................. 78 Programming Algorithm .............................................. 80 RTSP Operation ......................................................... 78 Table Instructions ....................................................... 77 Flexible Configuration ....................................................... 289 FSCM Delay for Crystal and PLL Clock Sources................... 86 Device Resets............................................................. 86 I I/O Ports............................................................................ 159 Parallel I/O (PIO) ...................................................... 159 Write/Read Timing .................................................... 160 I2C Addresses................................................................. 215 Baud Rate Generator ............................................... 213 General Call Address Support .................................. 215 Interrupts .................................................................. 213 IPMI Support............................................................. 215 Master Mode Operation Clock Arbitration ............................................... 216 Multi-Master Communication, Bus Collision and Bus Arbitration .................... 216 Operating Modes ...................................................... 213 Registers .................................................................. 213 Slave Address Masking ............................................ 215 Slope Control ............................................................ 216 Software Controlled Clock Stretching (STREN = 1) ..................................................... 215 I2C Module I2C1 Register Map...................................................... 53 I2C2 Register Map...................................................... 53 I2S Mode Operation .......................................................... 269 Data Justification ...................................................... 269 Frame and Data Word Length Selection .................. 269 In-Circuit Debugger........................................................... 295 In-Circuit Emulation .......................................................... 289 In-Circuit Serial Programming (ICSP)....................... 289, 295 Infrared Support Built-in IrDA Encoder and Decoder........................... 225 External IrDA, IrDA Clock Output ............................. 225 Input Capture Registers .................................................................. 170 Input Change Notification Module..................................... 160 Instruction Addressing Modes ............................................ 67 File Register Instructions ............................................ 67 Fundamental Modes Supported ................................. 68 MAC Instructions ........................................................ 68 MCU Instructions ........................................................ 67 Move and Accumulator Instructions............................ 68 Other Instructions ....................................................... 68 Instruction Set Overview................................................................... 300 Summary .................................................................. 297 E ECAN Module Baud Rate Setting..................................................... 236 ECAN1 Register Map (C1CTRL1.WIN = 0 or 1) ......... 58 ECAN1 Register Map (C1CTRL1.WIN = 0) ................ 58 ECAN1 Register Map (C1CTRL1.WIN = 1) ................ 59 ECAN2 Register Map (C2CTRL1.WIN = 0 or 1) ......... 61 ECAN2 Register Map (C2CTRL1.WIN = 0) .......... 61, 62 Frame Types ............................................................. 231 Message Reception .................................................. 233 Message Transmission ............................................. 235 Modes of Operation .................................................. 233 Overview ................................................................... 231 Electrical Characteristics................................................... 309 AC ............................................................................. 316 Enhanced CAN Module..................................................... 231 Equations A/D Conversion Clock Period ................................... 278 Bit Clock Frequency .................................................. 265 Calculating the PWM Period ..................................... 172 Calculation for Maximum PWM Resolution............... 172 COFSG Period .......................................................... 263 Device Operating Frequency .................................... 150 PWM Period .............................................................. 178 DS70165E-page 360 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F Instruction-Based Power-Saving Modes ........................... 157 Idle ............................................................................ 158 Sleep......................................................................... 157 Internal RC Oscillator Use with WDT ........................................................... 294 Internet Address................................................................ 365 Interrupt Control and Status Registers................................ 91 IECx ............................................................................ 91 IFSx............................................................................. 91 INTCON1 .................................................................... 91 INTCON2 .................................................................... 91 IPCx ............................................................................ 91 Interrupt Setup Procedures ............................................... 133 Initialization ............................................................... 133 Interrupt Disable........................................................ 133 Interrupt Service Routine .......................................... 133 Trap Service Routine ................................................ 133 Interrupt Vector Table (IVT) ................................................ 87 Interrupts Coincident with Power Save Instructions.......... 158 PICSTART Plus Development Programmer..................... 308 Pinout I/O Descriptions (table)............................................ 25 PMD Module Register Map .............................................................. 66 POR and Long Oscillator Start-up Times ........................... 86 PORTA Register Map .............................................................. 64 PORTB Register Map .............................................................. 64 PORTC Register Map .............................................................. 65 PORTD Register Map .............................................................. 65 PORTE Register Map .............................................................. 65 PORTF Register Map .............................................................. 65 PORTG Register Map .............................................................. 66 Power-Saving Features .................................................... 157 Clock Frequency and Switching ............................... 157 Program Address Space..................................................... 39 Construction ............................................................... 72 Data Access from Program Memory Using Program Space Visibility.................................... 75 Data Access from Program Memory Using Table Instructions ............................................... 74 Data Access from, Address Generation ..................... 73 Memory Map............................................................... 39 Table Read Instructions TBLRDH ............................................................. 74 TBLRDL.............................................................. 74 Visibility Operation...................................................... 75 Program Memory Interrupt Vector........................................................... 40 Organization ............................................................... 40 Reset Vector............................................................... 40 Pulse-Width Modulation Mode.......................................... 172 PWM Center-Aligned.......................................................... 179 Complementary Mode .............................................. 180 Complementary Output Mode .................................. 181 Duty Cycle ................................................................ 172 Edge-Aligned ............................................................ 178 Independent Output Mode........................................ 181 Operation During CPU Idle Mode............................. 183 Operation During CPU Sleep Mode ......................... 183 Output Override ........................................................ 181 Output Override Synchronization ............................. 182 Period ............................................................... 172, 178 Single Pulse Mode.................................................... 181 PWM Dead-Time Generators ........................................... 180 Assignment ............................................................... 181 Ranges ..................................................................... 181 Selection Bits (table)................................................. 181 PWM Duty Cycle Comparison Units ..................................................... 179 Immediate Updates .................................................. 179 Register Buffers........................................................ 179 PWM Fault Pins ................................................................ 182 Enable Bits ............................................................... 182 Fault States .............................................................. 182 Input Modes.............................................................. 183 Cycle-by-Cycle ................................................. 183 Latched............................................................. 183 J JTAG Boundary Scan Interface ........................................ 289 M Memory Organization.......................................................... 39 Microchip Internet Web Site .............................................. 365 Modes of Operation Disable ...................................................................... 233 Initialization ............................................................... 233 Listen All Messages .................................................. 233 Listen Only ................................................................ 233 Loopback .................................................................. 233 Normal Operation...................................................... 233 Modulo Addressing ............................................................. 68 Applicability ................................................................. 70 Operation Example ..................................................... 69 Start and End Address................................................ 69 W Address Register Selection .................................... 69 Motor Control PWM .......................................................... 175 Motor Control PWM Module 8-Output Register Map................................................ 52 MPLAB ASM30 Assembler, Linker, Librarian ................... 306 MPLAB ICD 2 In-Circuit Debugger ................................... 307 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator .................................................... 307 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator .................................................... 307 MPLAB Integrated Development Environment Software.................................................................... 305 MPLAB PM3 Device Programmer .................................... 307 MPLINK Object Linker/MPLIB Object Librarian ................ 306 N NVM Module Register Map............................................................... 66 O Open-Drain Configuration ................................................. 160 Output Compare ............................................................... 171 Registers................................................................... 174 P Packaging ......................................................................... 351 Details ....................................................................... 352 Marking ..................................................................... 351 Peripheral Module Disable (PMD) .................................... 158 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 361 dsPIC33F Priority ....................................................................... 182 PWM Output and Polarity Control ..................................... 182 Output Pin Control .................................................... 182 PWM Special Event Trigger .............................................. 183 Postscaler ................................................................. 183 PWM Time Base ............................................................... 177 Continuous Up/Down Count Modes.......................... 177 Double Update Mode ................................................ 178 Free-Running Mode .................................................. 177 Postscaler ................................................................. 178 Prescaler ................................................................... 178 Single-Shot Mode ..................................................... 177 PWM Update Lockout ....................................................... 183 CiRXMnEID (ECAN Acceptance Filter Mask n Extended Identifier) .......................................... 253 CiRXMnSID (ECAN Acceptance Filter Mask n Standard Identifier) ........................................... 253 CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 255 CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 255 CiTRBnDLC (ECAN Buffer n Data Length Control).. 258 CiTRBnDm (ECAN Buffer n Data Field Byte m) ....... 258 CiTRBnEID (ECAN Buffer n Extended Identifier) ..... 257 CiTRBnSID (ECAN Buffer n Standard Identifier)...... 257 CiTRBnSTAT (ECAN Receive Buffer n Status)........ 259 CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 256 CiVEC (ECAN Interrupt Code).................................. 240 CLKDIV (Clock Divisor) ............................................ 153 CORCON (Core Control) ...................................... 32, 92 DCICON1 (DCI Control 1) ........................................ 270 DCICON2 (DCI Control 2) ........................................ 271 DCICON3 (DCI Control 3) ........................................ 272 DCISTAT (DCI Status).............................................. 273 DFLTCON (QEI Control)........................................... 203 DMACS0 (DMA Controller Status 0)......................... 144 DMACS1 (DMA Controller Status 1)......................... 146 DMAxCNT (DMA Channel x Transfer Count) ........... 143 DMAxCON (DMA Channel x Control)....................... 140 DMAxPAD (DMA Channel x Peripheral Address) .... 143 DMAxREQ (DMA Channel x IRQ Select) ................. 141 DMAxSTA (DMA Channel x RAM Start Address A) . 142 DMAxSTB (DMA Channel x RAM Start Address B) . 142 DSADR (Most Recent DMA RAM Address) ............. 147 DTCON1 (Dead-Time Control 1) .............................. 189 DTCON2 (Dead-Time Control 2) .............................. 190 FLTACON (Fault A Control)...................................... 191 FLTBCON (Fault B Control)...................................... 192 I2CxCON (I2Cx Control) ........................................... 217 I2CxMSK (I2Cx Slave Mode Address Mask) ............ 221 I2CxSTAT (I2Cx Status) ........................................... 219 ICxCON (Input Capture x Control)............................ 170 IEC0 (Interrupt Enable Control 0) ............................. 105 IEC1 (Interrupt Enable Control 1) ............................. 107 IEC2 (Interrupt Enable Control 2) ............................. 109 IEC3 (Interrupt Enable Control 3) ............................. 111 IEC4 (Interrupt Enable Control 4) ............................. 113 IFS0 (Interrupt Flag Status 0) ..................................... 96 IFS1 (Interrupt Flag Status 1) ..................................... 98 IFS2 (Interrupt Flag Status 2) ................................... 100 IFS3 (Interrupt Flag Status 3) ................................... 102 IFS4 (Interrupt Flag Status 4) ................................... 104 INTCON1 (Interrupt Control 1).................................... 93 INTCON2 (Interrupt Control 2).................................... 95 INTTREG Interrupt Control and Status Register ...... 132 IPC0 (Interrupt Priority Control 0) ............................. 114 IPC1 (Interrupt Priority Control 1) ............................. 115 IPC10 (Interrupt Priority Control 10) ......................... 124 IPC11 (Interrupt Priority Control 11) ......................... 125 IPC12 (Interrupt Priority Control 12) ......................... 126 IPC13 (Interrupt Priority Control 13) ......................... 127 IPC14 (Interrupt Priority Control 14) ......................... 128 IPC15 (Interrupt Priority Control 15) ......................... 129 IPC16 (Interrupt Priority Control 16) ......................... 130 IPC17 (Interrupt Priority Control 17) ......................... 131 IPC2 (Interrupt Priority Control 2) ............................. 116 IPC3 (Interrupt Priority Control 3) ............................. 117 IPC4 (Interrupt Priority Control 4) ............................. 118 IPC5 (Interrupt Priority Control 5) ............................. 119 IPC6 (Interrupt Priority Control 6) ............................. 120 Q QEI 16-bit Up/Down Position Counter Mode.................... 198 Alternate 16-bit Timer/Counter.................................. 199 Count Direction Status .............................................. 198 Error Checking .......................................................... 198 Interrupts ................................................................... 200 Logic ......................................................................... 198 Operation During CPU Idle Mode ............................. 199 Operation During CPU Sleep Mode .......................... 199 Position Measurement Mode .................................... 198 Programmable Digital Noise Filters .......................... 199 Timer Operation During CPU Idle Mode ................... 200 Timer Operation During CPU Sleep Mode................ 199 Quadrature Encoder Interface (QEI) ................................. 197 Quadrature Encoder Interface (QEI) Module Register Map............................................................... 53 R Reader Response ............................................................. 366 Registers ADxCHS0 (ADCx Input Channel 0 Select................. 285 ADxCHS123 (ADCx Input Channel 1, 2, 3 Select) ... 284 ADxCON1 (ADCx Control 1) ..................................... 279 ADxCON2 (ADCx Control 2) ..................................... 281 ADxCON3 (ADCx Control 3) ..................................... 282 ADxCON4 (ADCx Control 4) ..................................... 283 ADxCSSH (ADCx Input Scan Select High) ............... 286 ADxCSSL (ADCx Input Scan Select Low) ................ 286 ADxPCFGH (ADCx Port Configuration High)............ 287 ADxPCFGL (ADCx Port Configuration Low) ............. 287 CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer)........... 248 CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer)........... 249 CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer)......... 249 CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer)....... 250 CiCFG1 (ECAN Baud Rate Configuration 1) ............ 246 CiCFG2 (ECAN Baud Rate Configuration 2) ............ 247 CiCTRL1 (ECAN Control 1) ...................................... 238 CiCTRL2 (ECAN Control 2) ...................................... 239 CiEC (ECAN Transmit/Receive Error Count)............ 245 CiFCTRL (ECAN FIFO Control) ................................ 241 CiFEN1 (ECAN Acceptance Filter Enable) ............... 248 CiFIFO (ECAN FIFO Status)..................................... 242 CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection) ...... 252 CiINTE (ECAN Interrupt Enable) .............................. 244 CiINTF (ECAN Interrupt Flag) ................................... 243 CiRXFnEID (ECAN Acceptance Filter n Extended Identifier)........................................... 251 CiRXFnSID (ECAN Acceptance Filter n Standard Identifier) ........................................... 251 CiRXFUL1 (ECAN Receive Buffer Full 1) ................. 254 CiRXFUL2 (ECAN Receive Buffer Full 2) ................. 254 DS70165E-page 362 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F IPC7 (Interrupt Priority Control 7) ............................. 121 IPC8 (Interrupt Priority Control 8) ............................. 122 IPC9 (Interrupt Priority Control 9) ............................. 123 NVMCOM (Flash Memory Control)............................. 79 OCxCON (Output Compare x Control) ..................... 174 OSCCON (Oscillator Control) ................................... 152 OSCTUN (FRC Oscillator Tuning) ............................ 155 OVDCON (Override Control) .................................... 193 PDC1 (PWM Duty Cycle 1)....................................... 194 PDC2 (PWM Duty Cycle 2)....................................... 194 PDC3 (PWM Duty Cycle 3)....................................... 195 PDC4 (PWM Duty Cycle 4)....................................... 195 PLLFBD (PLL Feedback Divisor).............................. 154 PTCON (PWM Time Base Control) .......................... 184 PTMR (PWM Timer Count Value)............................. 185 PTPER (PWM Time Base Period) ............................ 185 PWMCON1 (PWM Control 1) ................................... 187 PWMCON2 (PWM Control 2) ................................... 188 QEICON (QEI Control).............................................. 201 RCON (Reset Control) ................................................ 84 RSCON (DCI Receive Slot Control).......................... 274 SEVTCMP (Special Event Compare) ....................... 186 SPIxCON1 (SPIx Control 1)...................................... 210 SPIxCON2 (SPIx Control 2)...................................... 211 SPIxSTAT (SPIx Status and Control) ....................... 209 SR (CPU Status)................................................... 30, 92 T1CON (Timer1 Control)........................................... 162 TSCON (DCI Transmit Slot Control) ......................... 274 TxCON (T2CON, T4CON, T6CON or T8CON Control) ................................................ 166 TyCON (T3CON, T5CON, T7CON or T9CON Control) ................................................ 167 UxMODE (UARTx Mode).......................................... 226 UxSTA (UARTx Status and Control)......................... 228 Reset Clock Source Selection............................................... 85 Special Function Register Reset States ..................... 86 Times .......................................................................... 85 Reset Sequence ................................................................. 87 Resets ................................................................................. 83 Timing Characteristics CLKO and I/O ........................................................... 319 Timing Diagrams 10-bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000) .................................. 346 10-bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM = 1, SSRC = 111, SAMC = 00001) .......................................................... 347 S Serial Peripheral Interface (SPI) ....................................... 205 Setup for Continuous Output Pulse Generation................ 171 Setup for Single Output Pulse Generation ........................ 171 Software Simulator (MPLAB SIM)..................................... 306 Software Stack Pointer, Frame Pointer CALLL Stack Frame.................................................... 67 Special Features of the CPU ............................................ 289 SPI Master, Frame Master Connection ........................... 207 Master/Slave Connection.......................................... 207 Slave, Frame Master Connection ............................. 208 Slave, Frame Slave Connection ............................... 208 SPI Module SPI1 Register Map...................................................... 54 SPI2 Register Map...................................................... 54 Symbols Used in Opcode Descriptions............................. 298 System Control Register Map............................................................... 66 T Temperature and Voltage Specifications AC ............................................................................. 316 Timer1 ............................................................................... 161 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ..................... 163 12-bit A/D Conversion (ASAM = 0, SSRC = 000)..... 349 CAN I/O .................................................................... 343 Center-Aligned PWM................................................ 179 DCI AC-Link Mode.................................................... 341 DCI Multi -Channel, I2S Modes ................................ 339 Dead-Time................................................................ 180 ECAN Bit .................................................................. 236 Edge-Aligned PWM .................................................. 178 External Clock .......................................................... 317 Frame Sync, AC-Link Start-of-Frame ....................... 264 Frame Sync, Multi-Channel Mode ............................ 264 I2Cx Bus Data (Master Mode) .................................. 335 I2Cx Bus Data (Slave Mode) .................................... 337 I2Cx Bus Start/Stop Bits (Master Mode)................... 335 I2Cx Bus Start/Stop Bits (Slave Mode)..................... 337 I2S Interface Frame Sync ......................................... 264 Input Capture (CAPx) ............................................... 325 Motor Control PWM .................................................. 327 Motor Control PWM Fault ......................................... 327 OC/PWM .................................................................. 326 Output Compare (OCx) ............................................ 325 QEA/QEB Input ........................................................ 328 QEI Module Index Pulse........................................... 329 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer............................... 320 SPIx Master Mode (CKE = 0) ................................... 330 SPIx Master Mode (CKE = 1) ................................... 331 SPIx Slave Mode (CKE = 0) ..................................... 332 SPIx Slave Mode (CKE = 1) ..................................... 333 Timer1, 2, 3, 4, 5, 6, 7, 8, 9 External Clock .............. 322 TimerQ (QEI Module) External Clock ....................... 324 Timing Requirements CLKO and I/O ........................................................... 319 DCI AC-Link Mode.................................................... 342 DCI Multi-Channel, I2S Modes ................................. 340 External Clock .......................................................... 317 Input Capture............................................................ 325 Timing Specifications 10-bit A/D Conversion Requirements ....................... 348 12-bit A/D Conversion Requirements ....................... 350 CAN I/O Requirements............................................. 343 I2Cx Bus Data Requirements (Master Mode)........... 336 I2Cx Bus Data Requirements (Slave Mode)............. 338 Motor Control PWM Requirements........................... 327 Output Compare Requirements................................ 325 PLL Clock ................................................................. 318 QEI External Clock Requirements............................ 324 QEI Index Pulse Requirements ................................ 329 Quadrature Decoder Requirements ......................... 328 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements......................................... 321 Simple OC/PWM Mode Requirements ..................... 326 SPIx Master Mode (CKE = 0) Requirements............ 330 SPIx Master Mode (CKE = 1) Requirements............ 331 SPIx Slave Mode (CKE = 0) Requirements.............. 332 SPIx Slave Mode (CKE = 1) Requirements.............. 334 Timer1 External Clock Requirements ....................... 322 (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 363 dsPIC33F Timer2, Timer4, Timer6 and Timer8 External Clock Requirements.......................................... 323 Timer3, Timer5, Timer7 and Timer9 External Clock Requirements.......................................... 323 U UART Baud Rate Generator (BRG)............................................... 224 Break and Sync Transmit Sequence ........................ 225 Flow Control Using UxCTS and UxRTS Pins............ 225 Receiving in 8-bit or 9-bit Data Mode........................ 225 Transmitting in 8-bit Data Mode ................................ 225 Transmitting in 9-bit Data Mode ................................ 225 UART Module UART1 Register Map .................................................. 54 UART2 Register Map .................................................. 54 V Voltage Regulator (On-Chip)............................................. 293 W Watchdog Timer (WDT) ............................................ 289, 294 Programming Considerations ................................... 294 WWW Address.................................................................. 365 WWW, On-Line Support...................................................... 21 DS70165E-page 364 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 365 dsPIC33F READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: dsPIC33F Questions: 1. What are the best features of this document? Y N Literature Number: DS70165E FAX: (______) _________ - _________ 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70165E-page 366 Preliminary (c) 2007 Microchip Technology Inc. dsPIC33F PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 256 GP7 10 T I / PT - XXX Microchip Trademark Architecture Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern b) Examples: a) dsPIC33FJ256GP710I/PT: General-purpose dsPIC33, 64 KB program memory, 100-pin, Industrial temp., TQFP package. dsPIC33FJ64MC706I/PT-ES: Motor-control dsPIC33, 64 KB program memory, 64-pin, Industrial temp., TQFP package, Engineering Sample. Architecture: 33 = 16-bit Digital Signal Controller Flash Memory Family: FJ = Flash program memory, 3.3V Product Group: GP2 GP3 GP5 GP7 MC5 MC7 = = = = = = General purpose family General purpose family General purpose family General purpose family Motor control family Motor control family Pin Count: 06 08 10 = = = 64-pin 80-pin 100-pin Temperature Range: I = -40C to +85C (Industrial) Package: PT PF = = 10x10 or 12x12 mmTQFP (Thin Quad Flatpack) 14x14 mmTQFP (Thin Quad Flatpack) (c) 2007 Microchip Technology Inc. Preliminary DS70165E-page 367 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256 ASIA/PACIFIC India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 12/08/06 DS70165E-page 368 Preliminary (c) 2007 Microchip Technology Inc. |
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